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/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/
H A D0001-platform-corstone1000-Update-MPU-configuration.patch4 Subject: [PATCH 1/2] platform: corstone1000: Update MPU configuration
6 In Armv6-M the MPU requires the regions to be aligned with
10 multiple MPU regions in order to save memory.
17 Added checks to the MPU configuration function for checking the
18 MPU constraints:
20 - The minimum MPU region size is 0x100
21 - The MPU can have 8 regions at most
44 +# The Armv6-M MPU requires that the MPU regions be aligned to the region sizes.
175 + /* The MPU region's base address has to be aligned to the region
176 + * size for a valid MPU configuration */
[all …]
H A D0002-platform-corstone1000-Cover-S_DATA-with-MPU.patch4 Subject: [PATCH 2/2] platform: corstone1000: Cover S_DATA with MPU
6 The S_DATA has to be covered with MPU regions to override the
7 other MPU regions with smaller RNR values.
27 + # The RAM MPU Region block sizes are calculated manually. The RAM has to be covered
28 + # with the MPU regions. These regions also have to be the power of 2 and
/openbmc/linux/arch/arm/
H A DKconfig-nommu57 bool 'Use the ARM v7 PMSA Compliant MPU'
62 Unit (MPU) that defines the type and permissions for regions of
65 If your CPU has an MPU then you should choose 'y' here unless you
66 know that you do not want to use the MPU.
/openbmc/linux/Documentation/devicetree/bindings/arm/omap/
H A Dmpu.txt1 * TI - MPU (Main Processor Unit) subsystem
3 The MPU subsystem contain one or several ARM cores
5 The MPU contain CPUs, GIC, L2 cache and a local PRCM.
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Domap-dmic.txt6 <MPU access base address, size>,
15 reg = <0x4012e000 0x7f>, /* MPU private access */
H A Domap-mcpdm.txt6 <MPU access base address, size>,
17 reg = <0x40132000 0x7f>, /* MPU private access */
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-j721s2-mcu-wakeup.dtsi108 /* Non-MPU Firmware usage */
119 /* Non-MPU Firmware usage */
160 /* Non-MPU Firmware usage */
174 /* Non-MPU Firmware usage */
188 /* Non-MPU Firmware usage */
202 /* Non-MPU Firmware usage */
216 /* Non-MPU Firmware usage */
230 /* Non-MPU Firmware usage */
244 /* Non-MPU Firmware usage */
258 /* Non-MPU Firmware usage */
[all …]
H A Dk3-j784s4-mcu-wakeup.dtsi125 /* Non-MPU Firmware usage */
136 /* Non-MPU Firmware usage */
164 /* Non-MPU Firmware usage */
179 /* Non-MPU Firmware usage */
193 /* Non-MPU Firmware usage */
207 /* Non-MPU Firmware usage */
221 /* Non-MPU Firmware usage */
235 /* Non-MPU Firmware usage */
249 /* Non-MPU Firmware usage */
263 /* Non-MPU Firmware usage */
[all …]
H A Dk3-j721e-mcu-wakeup.dtsi72 /* Non-MPU Firmware usage */
83 /* Non-MPU Firmware usage */
105 /* Non-MPU Firmware usage */
119 /* Non-MPU Firmware usage */
133 /* Non-MPU Firmware usage */
147 /* Non-MPU Firmware usage */
161 /* Non-MPU Firmware usage */
175 /* Non-MPU Firmware usage */
189 /* Non-MPU Firmware usage */
203 /* Non-MPU Firmware usage */
[all …]
/openbmc/linux/Documentation/arch/arm/omap/
H A Domap_pm.rst34 1. Set the maximum MPU wakeup latency::
87 set_max_mpu_wakeup_lat() function to constrain the MPU wakeup
92 /* Limit MPU wakeup latency */
119 CPUFreq expresses target MPU performance levels in terms of MPU
121 specialized cases to convert that input information (OPPs/MPU
/openbmc/linux/Documentation/devicetree/bindings/iio/gyroscope/
H A Dinvensense,mpu3050.yaml7 title: Invensense MPU-3050 Gyroscope
34 The MPU-3050 will pass through and forward the I2C signals from the
/openbmc/u-boot/board/bosch/shc/
H A DREADME82 MPU reference clock runs at 6 MHz
83 Setting MPU clock to 594 MHz
84 Enabling Spread Spectrum of 18 permille for MPU
/openbmc/u-boot/board/siemens/pxm2/
H A Dboard.c88 #define MPU 0 macro
96 if (module == MPU) in voltage_update()
155 if (voltage_update(MPU, PMIC_OP_REG_SEL_1_2_6) || in spl_siemens_board_init()
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dwkup_m3_rproc.txt6 that cannot be controlled from the MPU. This CM3 processor requires a firmware
14 (l4_wkup) through which it is accessible to the MPU.
/openbmc/u-boot/arch/arm/mach-omap2/omap5/
H A DKconfig74 prompt "MPU Voltage Domain"
77 Select the Operating Performance Point(OPP) for the MPU voltage
83 This config option enables Normal OPP for MPU. This is the safest
/openbmc/u-boot/include/power/
H A Dtps65910.h11 #define MPU 0 macro
/openbmc/linux/Documentation/arch/arm/stm32/
H A Dstm32mp157-overview.rst8 The STM32MP157 is a Cortex-A MPU aimed at various applications.
H A Dstm32mp151-overview.rst8 The STM32MP151 is a Cortex-A MPU aimed at various applications.
H A Dstm32mp13-overview.rst8 The STM32MP131/STM32MP133/STM32MP135 are Cortex-A MPU aimed at various applications.
/openbmc/u-boot/doc/
H A DREADME.arm-caches21 - Flush the buffer after the MPU writes the data and before the DMA is
30 - Invalidate the buffer after the DMA is complete and before the MPU reads
/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-m/
H A Dtrusted-firmware-m-corstone1000.inc36 file://0001-platform-corstone1000-Update-MPU-configuration.patch \
37 file://0002-platform-corstone1000-Cover-S_DATA-with-MPU.patch \
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Dst,stm32mp1.txt25 MPU AXI MCU PLL12 PLL3 PLL4 RTC MCO1 MCO2
32 MPU AXI MCU APB1 APB2 APB3 APB4 APB5 RTC MCO1 MCO2
117 1 /*MPU*/
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dti,pruss-intc.yaml20 including the MPU and/or other PRUSS instances, DSPs or devices.
94 connected to MPU
96 "host_intr7" interrupts connected to MPU, and other ICSSG
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap5-l4-abe.dtsi109 reg = <0x0 0xff>, /* MPU private access */
144 reg = <0x0 0xff>, /* MPU private access */
179 reg = <0x0 0xff>, /* MPU private access */
233 reg = <0x0 0x7f>, /* MPU private access */
276 reg = <0x0 0x7f>, /* MPU private access */
/openbmc/u-boot/drivers/power/pmic/
H A Dpmic_tps65910.c85 if (module == MPU) in tps65910_voltage_update()

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