xref: /openbmc/u-boot/include/power/tps65910.h (revision d94604d5)
183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */
2b04601a7SPhilip, Avinash /*
3b04601a7SPhilip, Avinash  * (C) Copyright 2011-2013
4b04601a7SPhilip, Avinash  * Texas Instruments, <www.ti.com>
5b04601a7SPhilip, Avinash  *
6b04601a7SPhilip, Avinash  * For more details, please see the TRM at http://www.ti.com/product/tps65910
7b04601a7SPhilip, Avinash  */
8b04601a7SPhilip, Avinash #ifndef __POWER_TPS65910_H__
9b04601a7SPhilip, Avinash #define __POWER_TPS65910_H__
10b04601a7SPhilip, Avinash 
11b04601a7SPhilip, Avinash #define MPU     0
12b04601a7SPhilip, Avinash #define CORE    1
13b04601a7SPhilip, Avinash 
14b04601a7SPhilip, Avinash #define TPS65910_SR_I2C_ADDR				0x12
15b04601a7SPhilip, Avinash #define TPS65910_CTRL_I2C_ADDR				0x2D
16b04601a7SPhilip, Avinash 
17b04601a7SPhilip, Avinash /* PMIC Register offsets */
18b04601a7SPhilip, Avinash enum {
19b04601a7SPhilip, Avinash 	TPS65910_VDD1_REG				= 0x21,
20b04601a7SPhilip, Avinash 	TPS65910_VDD1_OP_REG				= 0x22,
21b04601a7SPhilip, Avinash 	TPS65910_VDD2_REG				= 0x24,
22b04601a7SPhilip, Avinash 	TPS65910_VDD2_OP_REG				= 0x25,
23b04601a7SPhilip, Avinash 	TPS65910_DEVCTRL_REG				= 0x3F,
24b04601a7SPhilip, Avinash };
25b04601a7SPhilip, Avinash 
26b04601a7SPhilip, Avinash /* VDD2 & VDD1 control register (VDD2_REG & VDD1_REG) */
27b04601a7SPhilip, Avinash #define TPS65910_VGAIN_SEL_MASK				(0x3 << 6)
28b04601a7SPhilip, Avinash #define TPS65910_ILMAX_MASK				(0x1 << 5)
29b04601a7SPhilip, Avinash #define TPS65910_TSTEP_MASK				(0x7 << 2)
30b04601a7SPhilip, Avinash #define TPS65910_ST_MASK				(0x3)
31b04601a7SPhilip, Avinash 
32b04601a7SPhilip, Avinash #define TPS65910_REG_VGAIN_SEL_X1			(0x0 << 6)
33b04601a7SPhilip, Avinash #define TPS65910_REG_VGAIN_SEL_X1_0			(0x1 << 6)
34b04601a7SPhilip, Avinash #define TPS65910_REG_VGAIN_SEL_X3			(0x2 << 6)
35b04601a7SPhilip, Avinash #define TPS65910_REG_VGAIN_SEL_X4			(0x3 << 6)
36b04601a7SPhilip, Avinash 
37b04601a7SPhilip, Avinash #define TPS65910_REG_ILMAX_1_0_A			(0x0 << 5)
38b04601a7SPhilip, Avinash #define TPS65910_REG_ILMAX_1_5_A			(0x1 << 5)
39b04601a7SPhilip, Avinash 
40b04601a7SPhilip, Avinash #define TPS65910_REG_TSTEP_				(0x0 << 2)
41b04601a7SPhilip, Avinash #define TPS65910_REG_TSTEP_12_5				(0x1 << 2)
42b04601a7SPhilip, Avinash #define TPS65910_REG_TSTEP_9_4				(0x2 << 2)
43b04601a7SPhilip, Avinash #define TPS65910_REG_TSTEP_7_5				(0x3 << 2)
44b04601a7SPhilip, Avinash #define TPS65910_REG_TSTEP_6_25				(0x4 << 2)
45b04601a7SPhilip, Avinash #define TPS65910_REG_TSTEP_4_7				(0x5 << 2)
46b04601a7SPhilip, Avinash #define TPS65910_REG_TSTEP_3_12				(0x6 << 2)
47b04601a7SPhilip, Avinash #define TPS65910_REG_TSTEP_2_5				(0x7 << 2)
48b04601a7SPhilip, Avinash 
49b04601a7SPhilip, Avinash #define TPS65910_REG_ST_OFF				(0x0)
50b04601a7SPhilip, Avinash #define TPS65910_REG_ST_ON_HI_POW			(0x1)
51b04601a7SPhilip, Avinash #define TPS65910_REG_ST_OFF_1				(0x2)
52b04601a7SPhilip, Avinash #define TPS65910_REG_ST_ON_LOW_POW			(0x3)
53b04601a7SPhilip, Avinash 
54b04601a7SPhilip, Avinash 
55b04601a7SPhilip, Avinash /* VDD2 & VDD1 voltage selection register. (VDD2_OP_REG & VDD1_OP_REG) */
56b04601a7SPhilip, Avinash #define TPS65910_OP_REG_SEL				(0x7F)
57b04601a7SPhilip, Avinash 
58b04601a7SPhilip, Avinash #define TPS65910_OP_REG_CMD_MASK			(0x1 << 7)
59b04601a7SPhilip, Avinash #define TPS65910_OP_REG_CMD_OP				(0x0 << 7)
60b04601a7SPhilip, Avinash #define TPS65910_OP_REG_CMD_SR				(0x1 << 7)
61b04601a7SPhilip, Avinash 
62b04601a7SPhilip, Avinash #define TPS65910_OP_REG_SEL_MASK			(0x7F)
63b04601a7SPhilip, Avinash #define TPS65910_OP_REG_SEL_0_9_5			(0x1F)	/* 0.9500 V */
6459041a50SLokesh Vutla #define TPS65910_OP_REG_SEL_1_1_0			(0x2B)	/* 1.1000 V */
65b04601a7SPhilip, Avinash #define TPS65910_OP_REG_SEL_1_1_3			(0x2E)	/* 1.1375 V */
66b04601a7SPhilip, Avinash #define TPS65910_OP_REG_SEL_1_2_0			(0x33)	/* 1.2000 V */
67b04601a7SPhilip, Avinash #define TPS65910_OP_REG_SEL_1_2_6			(0x38)	/* 1.2625 V */
68b04601a7SPhilip, Avinash #define TPS65910_OP_REG_SEL_1_3_2_5			(0x3D)	/* 1.3250 V */
69b04601a7SPhilip, Avinash 
70b04601a7SPhilip, Avinash /* Device control register . (DEVCTRL_REG) */
71b04601a7SPhilip, Avinash #define TPS65910_DEVCTRL_REG_SR_CTL_I2C_MASK		(0x1 << 4)
72b04601a7SPhilip, Avinash #define TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_SR_I2C	(0x0 << 4)
73b04601a7SPhilip, Avinash #define TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C	(0x1 << 4)
74b04601a7SPhilip, Avinash 
75*fb1b7712SJean-Jacques Hiblot int power_tps65910_init(unsigned char bus);
76b04601a7SPhilip, Avinash int tps65910_set_i2c_control(void);
77b04601a7SPhilip, Avinash int tps65910_voltage_update(unsigned int module, unsigned char vddx_op_vol_sel);
78b04601a7SPhilip, Avinash #endif	/* __POWER_TPS65910_H__ */
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