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Searched refs:MISS (Results 1 – 9 of 9) sorted by relevance

/openbmc/linux/drivers/net/ethernet/amd/
H A Dariadne.c285 if (csr0 & MISS) in ariadne_interrupt()
368 if (csr0 & MISS) { in ariadne_interrupt()
383 lance->RDP = INEA | BABL | CERR | MISS | MERR | IDON; in ariadne_interrupt()
H A Dariadne.h182 #define MISS 0x0010 /* Missed Frame */ macro
/openbmc/qemu/hw/arm/
H A Dtrace-events20 …mid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache MISS asid=%d vmid=%d add…
49 …int32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache MISS for sid=0x%x (hits=…
/openbmc/linux/arch/powerpc/perf/
H A Disa207-common.h276 #define PM(a, b) (P(LVL, MISS) | P(a, b))
/openbmc/linux/arch/x86/events/intel/
H A Dds.c76 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
80 P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
85 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
190 val |= P(TLB, MISS); in precise_store_data()
202 val |= P(LVL, MISS); in precise_store_data()
249 *val |= P(TLB, MISS) | P(TLB, L2); in pebs_set_tlb_lock()
H A Dp4.c98 P4_ESCR_EMASK_BIT(P4_EVENT_ITLB_REFERENCE, MISS) |
549 [ C(RESULT_MISS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_ITLB_REFERENCE, MISS,
/openbmc/linux/tools/perf/util/
H A Dmem-events.c636 if ((lvl & P(LVL, MISS))) in c2c_decode_stats()
652 if (lvl & P(LVL, MISS)) in c2c_decode_stats()
/openbmc/linux/Documentation/admin-guide/device-mapper/
H A Dcache-policies.rst12 The policy can return a simple HIT or MISS or issue a migration.
/openbmc/linux/arch/x86/include/asm/
H A Dperf_event_p4.h606 P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, MISS, 1),