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Searched refs:MDCNFG (Results 1 – 9 of 9) sorted by relevance

/openbmc/u-boot/arch/arm/cpu/pxa/
H A Dpxa2xx.c138 ~(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3), MDCNFG); in pxa2xx_dram_init()
159 tmp |= readl(MDCNFG); in pxa2xx_dram_init()
160 writelrb(tmp, MDCNFG); in pxa2xx_dram_init()
/openbmc/linux/arch/arm/mach-sa1100/
H A Dsleep.S102 ldr r9, =MDCNFG
130 @ Step 4 clear DE bis in MDCNFG
/openbmc/linux/arch/arm/mach-pxa/
H A Dpxa2xx.c40 mdcnfg = readl_relaxed(MDCNFG); in pxa2xx_smemc_get_sdram_rows()
H A Dsmemc.h15 #define MDCNFG (SMEMC_VIRT + 0x00) /* SDRAM Configuration Register 0 */ macro
/openbmc/linux/drivers/cpufreq/
H A Dsa1110-cpufreq.c162 sd->mdcnfg = MDCNFG & 0x007f007f; in sdram_calculate_timing()
291 : "r" (&MDCNFG), "r" (&PPCR), "0" (sd.mdcnfg), in sa1110_target()
/openbmc/linux/arch/arm/common/
H A Dsa1111.c886 FExtr(MDCNFG, MDCNFG_SA1110_DRAC0), in __sa1111_probe()
887 FExtr(MDCNFG, MDCNFG_SA1110_TDL0)); in __sa1111_probe()
/openbmc/u-boot/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2286 #define MDCNFG 0x48100000 /* SDRAM Configuration Register 0 */ macro
2443 #define MDCNFG 0x48000000 /* SDRAM Configuration Register 0 */ macro
/openbmc/u-boot/include/
H A DSA-1100.h1824 #define MDCNFG /* DRAM CoNFiGuration reg. */ \ macro
1834 #define MDCNFG (io_p2v(_MDCNFG)) macro
/openbmc/linux/arch/arm/mach-sa1100/include/mach/
H A DSA-1100.h1368 #define MDCNFG __REG(0xA0000000) /* DRAM CoNFiGuration reg. */ macro