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Searched refs:MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_0_sh_mask.h3033 #define MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20 macro
H A Dgmc_8_2_sh_mask.h3907 #define MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20 macro
H A Dgmc_6_0_sh_mask.h1580 #define MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x00000020L macro
H A Dgmc_7_1_sh_mask.h3653 #define MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20 macro
H A Dgmc_8_1_sh_mask.h4065 #define MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20 macro