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Searched refs:MC_CGM0_BASE_ADDR (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/board/freescale/s32v234evb/
H A Dclock.c200 CGM_SC_DCn(MC_CGM0_BASE_ADDR, 0)); in setup_sys_clocks()
204 CGM_SC_DCn(MC_CGM0_BASE_ADDR, 1)); in setup_sys_clocks()
217 aux_div_clk_config(MC_CGM0_BASE_ADDR, 5, 0, 4); in setup_aux_clocks()
221 aux_div_clk_config(MC_CGM0_BASE_ADDR, 3, 0, 1); in setup_aux_clocks()
224 aux_source_clk_config(MC_CGM0_BASE_ADDR, 7, MC_CGM_ACn_SEL_ENETPLL); in setup_aux_clocks()
225 aux_div_clk_config(MC_CGM0_BASE_ADDR, 7, 1, 9); in setup_aux_clocks()
232 aux_source_clk_config(MC_CGM0_BASE_ADDR, 15, MC_CGM_ACn_SEL_ENETPLL); in setup_aux_clocks()
233 aux_div_clk_config(MC_CGM0_BASE_ADDR, 15, 0, 9); in setup_aux_clocks()
236 aux_source_clk_config(MC_CGM0_BASE_ADDR, 8, MC_CGM_ACn_SEL_DDRPLL); in setup_aux_clocks()
237 aux_div_clk_config(MC_CGM0_BASE_ADDR, 8, 0, 0); in setup_aux_clocks()
[all …]
/openbmc/u-boot/arch/arm/cpu/armv8/s32v234/
H A Dgeneric.c145 sysclk_sel = readl(CGM_SC_SS(MC_CGM0_BASE_ADDR)) & MC_CGM_SC_SEL_MASK; in get_sys_clk()
181 readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 5, 0)) & in get_peripherals_clk()
197 readl(CGM_ACn_SS(MC_CGM0_BASE_ADDR, 3)) & MC_CGM_ACn_SEL_MASK; in get_uart_clk()
201 readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 3, 0)) & in get_uart_clk()
232 readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 2, 0)) & in get_fec_clk()
248 readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 15, 0)) & in get_usdhc_clk()
/openbmc/u-boot/arch/arm/include/asm/arch-s32v234/
H A Dmc_cgm_regs.h70 #define PLLDIG_PLLDV(pll) ((MC_CGM0_BASE_ADDR + 0x00000028) + ((pll) * 0x80))
94 #define PLLDIG_PLLFD(pll) ((MC_CGM0_BASE_ADDR + 0x00000030) + ((pll) * 0x80))
100 #define PLLDIG_PLLCAL1(pll) ((MC_CGM0_BASE_ADDR + 0x00000038) + ((pll) * 0x80))
107 #define DFS0_BASE_ADDR (MC_CGM0_BASE_ADDR + 0x00000040)
H A Dimx-regs.h39 #define MC_CGM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003C000) macro