Lines Matching refs:MC_CGM0_BASE_ADDR
200 CGM_SC_DCn(MC_CGM0_BASE_ADDR, 0)); in setup_sys_clocks()
204 CGM_SC_DCn(MC_CGM0_BASE_ADDR, 1)); in setup_sys_clocks()
216 aux_source_clk_config(MC_CGM0_BASE_ADDR, 5, MC_CGM_ACn_SEL_PERPLLDIVX); in setup_aux_clocks()
217 aux_div_clk_config(MC_CGM0_BASE_ADDR, 5, 0, 4); in setup_aux_clocks()
220 aux_source_clk_config(MC_CGM0_BASE_ADDR, 3, MC_CGM_ACn_SEL_PERPLLDIVX); in setup_aux_clocks()
221 aux_div_clk_config(MC_CGM0_BASE_ADDR, 3, 0, 1); in setup_aux_clocks()
224 aux_source_clk_config(MC_CGM0_BASE_ADDR, 7, MC_CGM_ACn_SEL_ENETPLL); in setup_aux_clocks()
225 aux_div_clk_config(MC_CGM0_BASE_ADDR, 7, 1, 9); in setup_aux_clocks()
232 aux_source_clk_config(MC_CGM0_BASE_ADDR, 15, MC_CGM_ACn_SEL_ENETPLL); in setup_aux_clocks()
233 aux_div_clk_config(MC_CGM0_BASE_ADDR, 15, 0, 9); in setup_aux_clocks()
236 aux_source_clk_config(MC_CGM0_BASE_ADDR, 8, MC_CGM_ACn_SEL_DDRPLL); in setup_aux_clocks()
237 aux_div_clk_config(MC_CGM0_BASE_ADDR, 8, 0, 0); in setup_aux_clocks()
239 aux_div_clk_config(MC_CGM0_BASE_ADDR, 8, 1, 3); in setup_aux_clocks()