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Searched refs:MCHBAR_REG (Results 1 – 9 of 9) sorted by relevance

/openbmc/u-boot/arch/x86/cpu/ivybridge/
H A Dnorthbridge.c114 bridge_type = readl(MCHBAR_REG(0x5f10)); in northbridge_init()
119 clrsetbits_8(MCHBAR_REG(0x5418), 0xf, 0x4); in northbridge_init()
127 writel(bridge_type, MCHBAR_REG(0x5f10)); in northbridge_init()
133 setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 1); in northbridge_init()
147 writel(msr.lo, MCHBAR_REG(0x59A0)); in northbridge_init()
148 writel(msr.hi, MCHBAR_REG(0x59A4)); in northbridge_init()
152 writel(0x00100001, MCHBAR_REG(0x5500)); in northbridge_init()
196 writel(IOMMU_BASE1 >> 32, MCHBAR_REG(0x5404)); in sandybridge_init_iommu()
197 writel(IOMMU_BASE1 | 1, MCHBAR_REG(0x5400)); in sandybridge_init_iommu()
198 writel(IOMMU_BASE2 >> 32, MCHBAR_REG(0x5414)); in sandybridge_init_iommu()
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H A Dcpu.c136 if (readl(MCHBAR_REG(SSKPD)) == 0xCAFE) { in checkcpu()
H A Dsdram.c198 setbits_le32(MCHBAR_REG(0x7010), 1); in post_system_agent_init()
551 writew(0xCAFE, MCHBAR_REG(SSKPD)); in dram_init()
/openbmc/u-boot/drivers/video/
H A Divybridge_igd.c440 reg32 = readl(MCHBAR_REG(0x5998)); in gma_pm_init_pre_vbios()
696 reg32 = readl(MCHBAR_REG(0x5f00)); in sandybridge_setup_graphics()
698 writel(reg32, MCHBAR_REG(0x5f00)); in sandybridge_setup_graphics()
701 reg32 = readl(MCHBAR_REG(0x5f00)); in sandybridge_setup_graphics()
702 writel(reg32 | 1, MCHBAR_REG(0x5f00)); in sandybridge_setup_graphics()
705 reg32 = readl(MCHBAR_REG(0x5d14)); in sandybridge_setup_graphics()
707 writel(reg32, MCHBAR_REG(0x5d14)); in sandybridge_setup_graphics()
710 reg32 = readl(MCHBAR_REG(0x6120)); in sandybridge_setup_graphics()
712 writel(reg32, MCHBAR_REG(0x6120)); in sandybridge_setup_graphics()
714 reg32 = readl(MCHBAR_REG(0x5418)); in sandybridge_setup_graphics()
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H A Dbroadwell_igd.c593 rp1_gfx_freq = (readl(MCHBAR_REG(0x5998)) >> 8) & 0xff; in igd_pre_init()
/openbmc/u-boot/arch/x86/cpu/broadwell/
H A Dcpu.c171 if (!(readl(MCHBAR_REG(BIOS_MAILBOX_INTERFACE)) & in pcode_ready()
201 return readl(MCHBAR_REG(BIOS_MAILBOX_DATA)); in pcode_mailbox_read()
214 writel(data, MCHBAR_REG(BIOS_MAILBOX_DATA)); in pcode_mailbox_write()
311 writel(~0, MCHBAR_REG(BIOS_MAILBOX_DATA)); in calibrate_24mhz_bclk()
313 MCHBAR_REG(BIOS_MAILBOX_INTERFACE)); in calibrate_24mhz_bclk()
325 MCHBAR_REG(BIOS_MAILBOX_INTERFACE)); in calibrate_24mhz_bclk()
332 readl(MCHBAR_REG(BIOS_MAILBOX_DATA))); in calibrate_24mhz_bclk()
703 writel(limit.lo, MCHBAR_REG(MCH_PKG_POWER_LIMIT_LO)); in cpu_set_power_limits()
704 writel(limit.hi, MCHBAR_REG(MCH_PKG_POWER_LIMIT_HI)); in cpu_set_power_limits()
707 msr.lo = readl(MCHBAR_REG(MCH_DDR_POWER_LIMIT_LO)); in cpu_set_power_limits()
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H A Dpch.c446 clrsetbits_8(MCHBAR_REG(MCH_PAIR), 0x7, 0x4); /* Fixed Priority */ in systemagent_init()
452 setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 3); in systemagent_init()
/openbmc/u-boot/arch/x86/cpu/intel_common/
H A Dmrc.c101 addr_decoder_common = readl(MCHBAR_REG(0x5000)); in report_memory_config()
102 addr_decode_ch[0] = readl(MCHBAR_REG(0x5004)); in report_memory_config()
103 addr_decode_ch[1] = readl(MCHBAR_REG(0x5008)); in report_memory_config()
106 (readl(MCHBAR_REG(0x5e04)) * 13333 * 2 + 50) / 100); in report_memory_config()
240 version = readl(MCHBAR_REG(MCHBAR_PEI_VERSION)); in sdram_initialise()
/openbmc/u-boot/arch/x86/include/asm/
H A Dintel_regs.h12 #define MCHBAR_REG(reg) (MCH_BASE_ADDRESS + (reg)) macro