xref: /openbmc/u-boot/arch/x86/include/asm/intel_regs.h (revision e8f80a5a)
1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */
206d336ccSSimon Glass /*
306d336ccSSimon Glass  * Copyright (c) 2016 Google, Inc
406d336ccSSimon Glass  */
506d336ccSSimon Glass 
606d336ccSSimon Glass #ifndef __ASM_INTEL_REGS_H
706d336ccSSimon Glass #define __ASM_INTEL_REGS_H
806d336ccSSimon Glass 
906d336ccSSimon Glass /* Access the memory-controller hub */
1006d336ccSSimon Glass #define MCH_BASE_ADDRESS	0xfed10000
1106d336ccSSimon Glass #define MCH_BASE_SIZE		0x8000
1206d336ccSSimon Glass #define MCHBAR_REG(reg)		(MCH_BASE_ADDRESS + (reg))
1306d336ccSSimon Glass 
1450dd3da0SSimon Glass #define MCHBAR_PEI_VERSION	0x5034
1550dd3da0SSimon Glass #define MCH_PKG_POWER_LIMIT_LO	0x59a0
1650dd3da0SSimon Glass #define MCH_PKG_POWER_LIMIT_HI	0x59a4
1750dd3da0SSimon Glass #define MCH_DDR_POWER_LIMIT_LO	0x58e0
1850dd3da0SSimon Glass #define MCH_DDR_POWER_LIMIT_HI	0x58e4
1950dd3da0SSimon Glass 
20bb096b9fSSimon Glass /* Access the Root Complex Register Block */
21bb096b9fSSimon Glass #define RCB_BASE_ADDRESS	0xfed1c000
22bb096b9fSSimon Glass #define RCB_REG(reg)		(RCB_BASE_ADDRESS + (reg))
23bb096b9fSSimon Glass 
2450dd3da0SSimon Glass #define SOFT_RESET_CTRL		0x38f4
2550dd3da0SSimon Glass #define SOFT_RESET_DATA		0x38f8
2650dd3da0SSimon Glass 
2706d336ccSSimon Glass #endif
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