Searched refs:MCF_MBAR (Results 1 – 9 of 9) sorted by relevance
27 #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status reg */31 #define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */33 #define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl Reg */35 #define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pend */36 #define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */37 #define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */38 #define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */94 #define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */106 #define MCFSIM_PADDR (MCF_MBAR + 0x244)107 #define MCFSIM_PADAT (MCF_MBAR + 0x248)[all …]
25 #define MCFSIM_SIMR (MCF_MBAR + 0x03) /* SIM Config reg */26 #define MCFSIM_ICR1 (MCF_MBAR + 0x14) /* Intr Ctrl reg 1 */27 #define MCFSIM_ICR2 (MCF_MBAR + 0x15) /* Intr Ctrl reg 2 */28 #define MCFSIM_ICR3 (MCF_MBAR + 0x16) /* Intr Ctrl reg 3 */29 #define MCFSIM_ICR4 (MCF_MBAR + 0x17) /* Intr Ctrl reg 4 */30 #define MCFSIM_ICR5 (MCF_MBAR + 0x18) /* Intr Ctrl reg 5 */31 #define MCFSIM_ICR6 (MCF_MBAR + 0x19) /* Intr Ctrl reg 6 */32 #define MCFSIM_ICR7 (MCF_MBAR + 0x1a) /* Intr Ctrl reg 7 */44 #define MCFSIM_IMR (MCF_MBAR + 0x36) /* Interrupt Mask */47 #define MCFSIM_RSR (MCF_MBAR + 0x40) /* Reset Status */[all …]
27 #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */31 #define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */33 #define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl */36 #define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */37 #define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */77 #define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */79 #define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */81 #define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */92 #define MCFSIM_PADDR (MCF_MBAR + 0x244)93 #define MCFSIM_PADAT (MCF_MBAR + 0x248)[all …]
25 #define MCFSIM_SCR (MCF_MBAR + 0x04) /* SIM Config reg */36 #define MCFSIM_ISR (MCF_MBAR + 0x30) /* Intr Source */38 #define MCFSIM_PIWR (MCF_MBAR + 0x38) /* Intr Wakeup */39 #define MCFSIM_PIVR (MCF_MBAR + 0x3f) /* Intr Vector */47 #define MCFSIM_CSOR0 (MCF_MBAR + 0x44) /* CS0 Option */49 #define MCFSIM_CSOR1 (MCF_MBAR + 0x4c) /* CS1 Option */51 #define MCFSIM_CSOR2 (MCF_MBAR + 0x54) /* CS2 Option */53 #define MCFSIM_CSOR3 (MCF_MBAR + 0x5c) /* CS3 Option */55 #define MCFSIM_CSOR4 (MCF_MBAR + 0x64) /* CS4 Option */57 #define MCFSIM_CSOR5 (MCF_MBAR + 0x6c) /* CS5 Option */[all …]
14 #define IOMEMBASE MCF_MBAR64 #define MCFGPIO_PODR (MCF_MBAR + 0xA00)65 #define MCFGPIO_PDDR (MCF_MBAR + 0xA10)66 #define MCFGPIO_PPDR (MCF_MBAR + 0xA20)67 #define MCFGPIO_SETR (MCF_MBAR + 0xA20)68 #define MCFGPIO_CLRR (MCF_MBAR + 0xA30)88 #define MCFGPIO_PAR_FBCS (MCF_MBAR + 0xA42)89 #define MCFGPIO_PAR_DMA (MCF_MBAR + 0xA43)93 #define MCFGPIO_PAR_PSC0 (MCF_MBAR + 0xA4F)94 #define MCFGPIO_PAR_PSC1 (MCF_MBAR + 0xA4E)[all …]
35 #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */38 #define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog srv */41 #define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */42 #define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */43 #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */44 #define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */45 #define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */56 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */71 #define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */73 #define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */[all …]
20 #define MCF_GPT_GMS0 (MCF_MBAR + 0x000800)21 #define MCF_GPT_GCIR0 (MCF_MBAR + 0x000804)22 #define MCF_GPT_GPWM0 (MCF_MBAR + 0x000808)23 #define MCF_GPT_GSR0 (MCF_MBAR + 0x00080C)24 #define MCF_GPT_GMS1 (MCF_MBAR + 0x000810)25 #define MCF_GPT_GCIR1 (MCF_MBAR + 0x000814)26 #define MCF_GPT_GPWM1 (MCF_MBAR + 0x000818)27 #define MCF_GPT_GSR1 (MCF_MBAR + 0x00081C)28 #define MCF_GPT_GMS2 (MCF_MBAR + 0x000820)29 #define MCF_GPT_GCIR2 (MCF_MBAR + 0x000824)[all …]
43 #define MCF_MBAR CONFIG_MBAR macro
145 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR))148 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr);