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Searched refs:MCFSIM_DCR (Results 1 – 9 of 9) sorted by relevance

/openbmc/u-boot/board/freescale/m5249evb/
H A Dm5249evb.c47 mbar_writeShort(MCFSIM_DCR, 0x8239); in dram_init()
53 mbar_writeShort(MCFSIM_DCR, 0x8202); in dram_init()
59 mbar_writeShort(MCFSIM_DCR, 0x8222); in dram_init()
/openbmc/u-boot/board/freescale/m5253demo/
H A Dm5253demo.c32 if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) { in dram_init()
39 mbar_writeShort(MCFSIM_DCR, (0x8400 | RC)); in dram_init()
/openbmc/u-boot/arch/m68k/include/asm/
H A Dm5249.h63 #define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ macro
/openbmc/linux/arch/m68k/include/asm/
H A Dm527xsim.h72 #define MCFSIM_DCR (MCF_IPSBAR + 0x40) /* Control */ macro
80 #define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */ macro
H A Dm5407sim.h77 #define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ macro
H A Dm5307sim.h94 #define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ macro
H A Dm523xsim.h63 #define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */ macro
H A Dm525xsim.h71 #define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ macro
H A Dm528xsim.h63 #define MCFSIM_DCR (MCF_IPSBAR + 0x00000044) /* Control */ macro