Searched refs:MCFSIM_DACR0 (Results 1 – 9 of 9) sorted by relevance
42 mbar_writeLong(MCFSIM_DACR0, 0x00003224); in dram_init()51 mbar_writeLong(MCFSIM_DACR0, 0x0000322c); in dram_init()61 mbar_writeLong(MCFSIM_DACR0, in dram_init()62 mbar_readLong(MCFSIM_DACR0) | 0x8000); in dram_init()69 mbar_writeLong(MCFSIM_DACR0, in dram_init()70 mbar_readLong(MCFSIM_DACR0) | 0x0040); in dram_init()
68 mbar_writeLong(MCFSIM_DACR0, 0x00003324); in dram_init()74 mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */ in dram_init()79 mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */ in dram_init()83 mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */ in dram_init()
64 #define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ macro
78 #define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */ macro
95 #define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM Addr/Ctrl 0 */ macro
64 #define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */ macro
72 #define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */ macro
64 #define MCFSIM_DACR0 (MCF_IPSBAR + 0x00000048) /* Base address 0 */ macro
73 #define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */ macro