| /openbmc/u-boot/board/freescale/mx6memcal/ |
| H A D | Kconfig | 88 Select the type of DDR (DDR3 or LPDDR2) used on your design
95 config LPDDR2 config in mx6memcal specifics""choicec87005010304
96 bool "LPDDR2"
98 Select this if your board design uses LPDDR2.
122 bool "Micron MT42L256M32D2LG LPDDR2 256Mx32 (1GiB/chip)"
123 depends on LPDDR2
126 bool "Micron MT29PZZZ4D4BKESK multi-chip 512MiB LPDDR2/4GiB eMMC"
127 depends on LPDDR2
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| H A D | README | 35 4. The type of DDR (DDR3 or LPDDR2). Note that LPDDR2 support
38 parts and four DDR3 and two LPDDR2 parts are currently defined
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| /openbmc/linux/drivers/mtd/lpddr/ |
| H A D | Kconfig | 2 menu "LPDDR & LPDDR2 PCM memory drivers"
25 tristate "Support for LPDDR2-NVM flash chips"
27 This option enables support of PCM memories with a LPDDR2-NVM
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| /openbmc/linux/Documentation/driver-api/memory-devices/ |
| H A D | ti-emif.rst | 30 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
31 This driver takes care of only LPDDR2 memories presently. The
63 - mr4 : last polled value of MR4 register in the LPDDR2 device. MR4
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| /openbmc/u-boot/drivers/ram/stm32mp1/ |
| H A D | Kconfig | 10 family: support for LPDDR2, LPDDR3 and DDR3
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| /openbmc/u-boot/doc/device-tree-bindings/memory-controllers/ |
| H A D | st,stm32mp1-ddr.txt | 1 ST,stm32mp1 DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL and DDRPHYC)
26 (DDR3/LPDDR2/LPDDR3)
104 - st,phy-reg : phy values depending of the DDR type (DDR3/LPDDR2/LPDDR3)
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| /openbmc/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | sdram_rk3399.h | 11 LPDDR2 = 0x5, enumerator
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| H A D | sdram_rk322x.h | 12 LPDDR2 = 5, enumerator
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| /openbmc/linux/drivers/cpufreq/ |
| H A D | s5pv210-cpufreq.c | 115 LPDDR2 = 0x2, enumerator
530 if ((mem_type != LPDDR) && (mem_type != LPDDR2)) { in s5pv210_cpu_init()
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| /openbmc/linux/arch/arm/boot/dts/nvidia/ |
| H A D | tegra30-asus-tf201.dts | 113 /* Elpida 1GB EDB8132B2MA-8D-F LPDDR2 400MHz */
168 /* TF201 Unknown 1GB LPDDR2 500MHZ */
225 /* Elpida 1GB EDB8132B2MA-8D-F LPDDR2 400MHz */
405 /* TF201 Unknown 1GB LPDDR2 500MHZ */
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| /openbmc/u-boot/drivers/ram/rockchip/ |
| H A D | sdram_rk322x.c | 446 if (dramtype == LPDDR2) { in pctl_cfg()
488 case LPDDR2: in phy_cfg()
502 if (sdram_params->base.dramtype == LPDDR2) in phy_cfg()
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| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ddr/ |
| H A D | jedec,lpddr2-timings.yaml | 7 title: LPDDR2 SDRAM AC timing parameters for a given speed-bin
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| H A D | jedec,lpddr2.yaml | 7 title: LPDDR2 SDRAM compliant to JEDEC JESD209-2
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| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ti/ |
| H A D | emif.txt | 5 DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
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| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | nvidia,tegra30-mc.yaml | 34 and arbitrates among them to allocate memory bandwidth for DDR3L and LPDDR2
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| H A D | nvidia,tegra20-emc.yaml | 19 standard protocols: DDR1, LPDDR2 and DDR2.
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| H A D | nvidia,tegra30-emc.yaml | 18 settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2,
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| /openbmc/u-boot/board/freescale/mx6qarm2/ |
| H A D | imximage_mx6dl.cfg | 148 /*LPDDR2 ZQ params */
192 * a. DQS gating is not relevant for LPDDR2. DSQ gating calibration section
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| /openbmc/linux/drivers/memory/ |
| H A D | Kconfig | 97 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
98 This driver takes care of only LPDDR2 memories presently. The
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| /openbmc/u-boot/board/ccv/xpress/ |
| H A D | imximage.cfg | 145 * a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT
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| /openbmc/u-boot/drivers/power/ |
| H A D | Kconfig | 179 On A31 boards aldo2 may be used for LPDDR2 then it should be 1.8V.
183 LPDDR2, and the codec. It should be 1.8V.
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