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Searched refs:LOG_UNIMP (Results 1 – 25 of 248) sorted by relevance

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/openbmc/qemu/hw/nvram/
H A Dbcm2835_otp.c40 qemu_log_mask(LOG_UNIMP, in bcm2835_otp_read()
44 qemu_log_mask(LOG_UNIMP, in bcm2835_otp_read()
48 qemu_log_mask(LOG_UNIMP, in bcm2835_otp_read()
52 qemu_log_mask(LOG_UNIMP, in bcm2835_otp_read()
56 qemu_log_mask(LOG_UNIMP, in bcm2835_otp_read()
60 qemu_log_mask(LOG_UNIMP, in bcm2835_otp_read()
64 qemu_log_mask(LOG_UNIMP, in bcm2835_otp_read()
68 qemu_log_mask(LOG_UNIMP, in bcm2835_otp_read()
72 qemu_log_mask(LOG_UNIMP, in bcm2835_otp_read()
76 qemu_log_mask(LOG_UNIMP, in bcm2835_otp_read()
[all …]
/openbmc/qemu/hw/ssi/
H A Dstm32f2xx_spi.c79 qemu_log_mask(LOG_UNIMP, "%s: Interrupts and DMA are not implemented\n", in stm32f2xx_spi_read()
89 qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \ in stm32f2xx_spi_read()
93 qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \ in stm32f2xx_spi_read()
97 qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \ in stm32f2xx_spi_read()
101 qemu_log_mask(LOG_UNIMP, "%s: I2S is not implemented, the registers " \ in stm32f2xx_spi_read()
105 qemu_log_mask(LOG_UNIMP, "%s: I2S is not implemented, the registers " \ in stm32f2xx_spi_read()
129 qemu_log_mask(LOG_UNIMP, "%s: " \ in stm32f2xx_spi_write()
143 qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented\n", __func__); in stm32f2xx_spi_write()
154 qemu_log_mask(LOG_UNIMP, "%s: " \ in stm32f2xx_spi_write()
158 qemu_log_mask(LOG_UNIMP, "%s: " \ in stm32f2xx_spi_write()
H A Dibex_spi_host.c376 qemu_log_mask(LOG_UNIMP, in ibex_spi_host_write()
389 qemu_log_mask(LOG_UNIMP, in ibex_spi_host_write()
396 qemu_log_mask(LOG_UNIMP, in ibex_spi_host_write()
431 qemu_log_mask(LOG_UNIMP, in ibex_spi_host_write()
436 qemu_log_mask(LOG_UNIMP, in ibex_spi_host_write()
440 qemu_log_mask(LOG_UNIMP, in ibex_spi_host_write()
477 qemu_log_mask(LOG_UNIMP, in ibex_spi_host_write()
500 qemu_log_mask(LOG_UNIMP, in ibex_spi_host_write()
537 qemu_log_mask(LOG_UNIMP, in ibex_spi_host_write()
541 qemu_log_mask(LOG_UNIMP, in ibex_spi_host_write()
[all …]
/openbmc/qemu/hw/char/
H A Dbcm2835_aux.c112 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_LCR_REG unsupported\n", __func__); in bcm2835_aux_read()
116 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_MCR_REG unsupported\n", __func__); in bcm2835_aux_read()
127 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_MSR_REG unsupported\n", __func__); in bcm2835_aux_read()
131 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_SCRATCH unsupported\n", __func__); in bcm2835_aux_read()
147 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_BAUD_REG unsupported\n", __func__); in bcm2835_aux_read()
166 qemu_log_mask(LOG_UNIMP, "%s: unsupported attempt to enable SPI" in bcm2835_aux_write()
193 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_LCR_REG unsupported\n", __func__); in bcm2835_aux_write()
197 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_MCR_REG unsupported\n", __func__); in bcm2835_aux_write()
201 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_SCRATCH unsupported\n", __func__); in bcm2835_aux_write()
205 qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_CNTL_REG unsupported\n", __func__); in bcm2835_aux_write()
[all …]
H A Dibex_uart.c317 qemu_log_mask(LOG_UNIMP, in ibex_uart_read()
323 qemu_log_mask(LOG_UNIMP, in ibex_uart_read()
328 qemu_log_mask(LOG_UNIMP, in ibex_uart_read()
333 qemu_log_mask(LOG_UNIMP, in ibex_uart_read()
370 qemu_log_mask(LOG_UNIMP, in ibex_uart_write()
374 qemu_log_mask(LOG_UNIMP, in ibex_uart_write()
378 qemu_log_mask(LOG_UNIMP, in ibex_uart_write()
382 qemu_log_mask(LOG_UNIMP, in ibex_uart_write()
387 qemu_log_mask(LOG_UNIMP, in ibex_uart_write()
392 qemu_log_mask(LOG_UNIMP, in ibex_uart_write()
[all …]
/openbmc/qemu/hw/misc/
H A Diotkit-sysctl.c402 qemu_log_mask(LOG_UNIMP, in iotkit_sysctl_write()
407 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl RESET_MASK unimplemented\n"); in iotkit_sysctl_write()
456 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl WICCTRL unimplemented\n"); in iotkit_sysctl_write()
469 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SECDBGSET unimplemented\n"); in iotkit_sysctl_write()
488 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SCSECCTRL unimplemented\n"); in iotkit_sysctl_write()
501 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl FCLK_DIV unimplemented\n"); in iotkit_sysctl_write()
514 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SYSCLK_DIV unimplemented\n"); in iotkit_sysctl_write()
527 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CLOCK_FORCE unimplemented\n"); in iotkit_sysctl_write()
553 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl EWCTRL unimplemented\n"); in iotkit_sysctl_write()
558 qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl NMI_ENABLE unimplemented\n"); in iotkit_sysctl_write()
[all …]
H A Dstm32l4x5_syscfg.c145 qemu_log_mask(LOG_UNIMP, in stm32l4x5_syscfg_write()
151 qemu_log_mask(LOG_UNIMP, in stm32l4x5_syscfg_write()
163 qemu_log_mask(LOG_UNIMP, in stm32l4x5_syscfg_write()
174 qemu_log_mask(LOG_UNIMP, in stm32l4x5_syscfg_write()
183 qemu_log_mask(LOG_UNIMP, in stm32l4x5_syscfg_write()
190 qemu_log_mask(LOG_UNIMP, in stm32l4x5_syscfg_write()
196 qemu_log_mask(LOG_UNIMP, in stm32l4x5_syscfg_write()
H A Dbcm2835_powermgt.c45 qemu_log_mask(LOG_UNIMP, in bcm2835_powermgt_read()
82 qemu_log_mask(LOG_UNIMP, in bcm2835_powermgt_write()
87 qemu_log_mask(LOG_UNIMP, in bcm2835_powermgt_write()
93 qemu_log_mask(LOG_UNIMP, in bcm2835_powermgt_write()
H A Dmchp_pfsoc_dmc.c78 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read " in mchp_pfsoc_ddr_sgmii_phy_read()
90 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write " in mchp_pfsoc_ddr_sgmii_phy_write()
161 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read " in type_init()
173 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write " in mchp_pfsoc_ddr_cfg_write()
H A Dmchp_pfsoc_ioscb.c70 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read " in mchp_pfsoc_dummy_read()
80 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write " in mchp_pfsoc_dummy_write()
107 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read " in mchp_pfsoc_pll_read()
137 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read " in mchp_pfsoc_io_calib_ddr_read()
173 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read " in mchp_pfsoc_ctrl_read()
191 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write " in mchp_pfsoc_ctrl_write()
H A Darm_integrator_debug.c39 qemu_log_mask(LOG_UNIMP, in intdbg_control_read()
59 qemu_log_mask(LOG_UNIMP, in intdbg_control_write()
H A Darmv7m_ras.c33 qemu_log_mask(LOG_UNIMP, "Read RAS register offset 0x%x\n", in ras_read()
51 qemu_log_mask(LOG_UNIMP, "Write to RAS register offset 0x%x\n", in ras_write()
H A Dmchp_pfsoc_sysreg.c47 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read " in mchp_pfsoc_sysreg_read()
70 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write " in mchp_pfsoc_sysreg_write()
H A Dunimp.c25 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read " in unimp_read()
36 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write " in unimp_write()
/openbmc/qemu/hw/adc/
H A Dstm32f2xx_adc.c108 qemu_log_mask(LOG_UNIMP, in stm32f2xx_adc_read()
127 qemu_log_mask(LOG_UNIMP, "%s: " \ in stm32f2xx_adc_read()
142 qemu_log_mask(LOG_UNIMP, "%s: " \ in stm32f2xx_adc_read()
150 qemu_log_mask(LOG_UNIMP, "%s: " \ in stm32f2xx_adc_read()
180 qemu_log_mask(LOG_UNIMP, in stm32f2xx_adc_write()
205 qemu_log_mask(LOG_UNIMP, "%s: " \ in stm32f2xx_adc_write()
226 qemu_log_mask(LOG_UNIMP, "%s: " \ in stm32f2xx_adc_write()
235 qemu_log_mask(LOG_UNIMP, "%s: " \ in stm32f2xx_adc_write()
/openbmc/qemu/hw/ppc/
H A Dpnv_adu.c51 qemu_log_mask(LOG_UNIMP, "ADU: LPC_BASE_REG is not implemented\n"); in pnv_adu_xscom_read()
64 qemu_log_mask(LOG_UNIMP, "ADU Unimplemented read register: Ox%08x\n", in pnv_adu_xscom_read()
108 qemu_log_mask(LOG_UNIMP, in pnv_adu_xscom_write()
156 qemu_log_mask(LOG_UNIMP, in pnv_adu_xscom_write()
161 qemu_log_mask(LOG_UNIMP, "ADU Unimplemented write register: Ox%08x\n", in pnv_adu_xscom_write()
H A Dpnv_n1_chiplet.c41 qemu_log_mask(LOG_UNIMP, "%s: Invalid xscom read at 0x%" PRIx32 "\n", in pnv_n1_chiplet_pb_scom_eq_read()
58 qemu_log_mask(LOG_UNIMP, "%s: Invalid xscom write at 0x%" PRIx32 "\n", in pnv_n1_chiplet_pb_scom_eq_write()
85 qemu_log_mask(LOG_UNIMP, "%s: Invalid xscom read at 0x%" PRIx32 "\n", in pnv_n1_chiplet_pb_scom_es_read()
102 qemu_log_mask(LOG_UNIMP, "%s: Invalid xscom write at 0x%" PRIx32 "\n", in pnv_n1_chiplet_pb_scom_es_write()
H A Dpnv_core.c94 qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, in pnv_core_power8_xscom_read()
106 qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, in pnv_core_power8_xscom_write()
151 qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, in pnv_core_power9_xscom_read()
168 qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, in pnv_core_power9_xscom_write()
227 qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, in pnv_core_power10_xscom_read()
281 qemu_log_mask(LOG_UNIMP, "%s: unimp bits in DIRECT_CONTROLS " in pnv_core_power10_xscom_write()
287 qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, in pnv_core_power10_xscom_write()
529 qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, in DEFINE_TYPES()
546 qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, in pnv_quad_power9_xscom_write()
573 qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, in pnv_quad_power10_xscom_read()
[all …]
H A Dpnv_homer.c64 qemu_log_mask(LOG_UNIMP, "PBA: read to unimplemented register: Ox%" in pnv_homer_power8_pba_read()
73 qemu_log_mask(LOG_UNIMP, "PBA: write to unimplemented register: Ox%" in pnv_homer_power8_pba_write()
131 qemu_log_mask(LOG_UNIMP, "PBA: read to unimplemented register: Ox%" in pnv_homer_power9_pba_read()
140 qemu_log_mask(LOG_UNIMP, "PBA: write to unimplemented register: Ox%" in pnv_homer_power9_pba_write()
198 qemu_log_mask(LOG_UNIMP, "PBA: read to unimplemented register: Ox%" in pnv_homer_power10_pba_read()
207 qemu_log_mask(LOG_UNIMP, "PBA: write to unimplemented register: Ox%" in pnv_homer_power10_pba_write()
H A Dpnv_sbe.c95 qemu_log_mask(LOG_UNIMP, "SBE Unimplemented register: Ox%" in pnv_sbe_power9_xscom_ctrl_read()
113 qemu_log_mask(LOG_UNIMP, "SBE Unimplemented register: Ox%" in pnv_sbe_power9_xscom_ctrl_write()
240 qemu_log_mask(LOG_UNIMP, "SBE Unimplemented command: 0x%x\n", cmd); in do_sbe_msg()
274 qemu_log_mask(LOG_UNIMP, "SBE Unimplemented register: Ox%" in pnv_sbe_power9_xscom_mbox_read()
318 qemu_log_mask(LOG_UNIMP, "SBE Unimplemented register: Ox%" in pnv_sbe_power9_xscom_mbox_write()
/openbmc/qemu/target/xtensa/
H A Dgdbstub.c105 qemu_log_mask(LOG_UNIMP, "%s from reg %d of unsupported size %d\n", in xtensa_cpu_gdb_read_register()
114 qemu_log_mask(LOG_UNIMP, "%s from reg %d of unsupported type %d\n", in xtensa_cpu_gdb_read_register()
164 qemu_log_mask(LOG_UNIMP, "%s to reg %d of unsupported size %d\n", in xtensa_cpu_gdb_write_register()
174 qemu_log_mask(LOG_UNIMP, "%s to reg %d of unsupported type %d\n", in xtensa_cpu_gdb_write_register()
/openbmc/qemu/linux-user/
H A Dfd-trans.c589 qemu_log_mask(LOG_UNIMP, "Unknown QEMU_IFLA_BR type %d\n", in host_to_target_data_bridge_nlattr()
657 qemu_log_mask(LOG_UNIMP, "Unknown QEMU_IFLA_BRPORT type %d\n", in host_to_target_slave_data_bridge_nlattr()
686 qemu_log_mask(LOG_UNIMP, "Unknown QEMU_IFLA_TUN type %d\n", in host_to_target_data_tun_nlattr()
734 qemu_log_mask(LOG_UNIMP, "Unknown QEMU_IFLA_INFO_KIND %s\n", in host_to_target_data_linkinfo_nlattr()
746 qemu_log_mask(LOG_UNIMP, "Unknown QEMU_IFLA_INFO_SLAVE_KIND %s\n", in host_to_target_data_linkinfo_nlattr()
751 qemu_log_mask(LOG_UNIMP, "Unknown host QEMU_IFLA_INFO type: %d\n", in host_to_target_data_linkinfo_nlattr()
774 qemu_log_mask(LOG_UNIMP, "Unknown host AF_INET type: %d\n", in host_to_target_data_inet_nlattr()
826 qemu_log_mask(LOG_UNIMP, "Unknown host AF_INET6 type: %d\n", in host_to_target_data_inet6_nlattr()
845 qemu_log_mask(LOG_UNIMP, "Unknown host AF_SPEC type: %d\n", in host_to_target_data_spec_nlattr()
868 LOG_UNIMP, "Unknown host XDP type: %d\n", nlattr->nla_type); in host_to_target_data_xdp_nlattr()
[all …]
/openbmc/qemu/hw/mem/
H A Dnpcm7xx_mc.c37 qemu_log_mask(LOG_UNIMP, "%s: mostly unimplemented\n", __func__); in npcm7xx_mc_read()
45 qemu_log_mask(LOG_UNIMP, "%s: mostly unimplemented\n", __func__); in npcm7xx_mc_write()
/openbmc/qemu/hw/gpio/
H A Dstm32l4x5_gpio.c269 qemu_log_mask(LOG_UNIMP, in stm32l4x5_gpio_write()
279 qemu_log_mask(LOG_UNIMP, in stm32l4x5_gpio_write()
290 qemu_log_mask(LOG_UNIMP, in stm32l4x5_gpio_write()
308 qemu_log_mask(LOG_UNIMP, in stm32l4x5_gpio_write()
314 qemu_log_mask(LOG_UNIMP, in stm32l4x5_gpio_write()
320 qemu_log_mask(LOG_UNIMP, in stm32l4x5_gpio_write()
332 qemu_log_mask(LOG_UNIMP, in stm32l4x5_gpio_write()
/openbmc/qemu/hw/m68k/
H A Dnext-kbd.c87 qemu_log_mask(LOG_UNIMP, "NeXT kbd read byte %"HWADDR_PRIx"\n", addr); in kbd_read_byte()
95 qemu_log_mask(LOG_UNIMP, "NeXT kbd read word %"HWADDR_PRIx"\n", addr); in kbd_read_word()
134 qemu_log_mask(LOG_UNIMP, "NeXT kbd read long %"HWADDR_PRIx"\n", addr); in kbd_read_long()
156 qemu_log_mask(LOG_UNIMP, "NeXT kbd write: size=%u addr=0x%"HWADDR_PRIx in kbd_writefn()

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