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Searched refs:LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/arch/arm/include/asm/mach-imx/
H A Dregs-lcdif.h219 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 24 macro
222 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18 macro
/openbmc/u-boot/drivers/video/
H A Dmxsfb.c104 writel((mode->hsync_len << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) | in mxs_lcd_init()
/openbmc/u-boot/arch/arm/include/asm/arch-mx7/
H A Dimx-regs.h1184 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18 macro