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Searched refs:LCCR3_VSP (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/video/fbdev/
H A Dpxa3xx-regs.h116 #define LCCR3_VSP (1 << 20) /* vertical sync polarity */ macro
136 #define LCCR3_VrtSnchH (LCCR3_VSP*0) /* VSP Active High */
137 #define LCCR3_VrtSnchL (LCCR3_VSP*1) /* VSP Active Low */
H A Dpxafb.c82 #define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\
1252 fbi->reg_lccr3 |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0; in setup_smart_timing()
/openbmc/linux/arch/arm/mach-sa1100/include/mach/
H A DSA-1100.h1780 #define LCCR3_VSP 0x00100000 /* Vertical Synchronization pulse */ macro
1782 #define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */
1784 #define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */
/openbmc/u-boot/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2180 #define LCCR3_VSP (1 << 20) /* vertical sync polarity */ macro
2209 #define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */
2211 #define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */
/openbmc/u-boot/drivers/video/
H A Dpxa_lcd.c547 fbi->reg_lccr3 = REG_LCCR3 & ~(LCCR3_HSP | LCCR3_VSP); in pxafb_init()
/openbmc/u-boot/include/
H A DSA-1100.h2811 #define LCCR3_VSP 0x00100000 /* Vertical Synchronization pulse */ macro
2813 #define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */
2815 #define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */