Searched refs:L1CSR1_ICLFR (Results 1 – 8 of 8) sorted by relevance
| /openbmc/u-boot/arch/powerpc/cpu/mpc85xx/ |
| H A D | release.S | 102 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
103 ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
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| H A D | start.S | 771 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
772 ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
931 lis r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
932 ori r3,r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
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| /openbmc/linux/arch/powerpc/mm/nohash/ |
| H A D | e500.c | 248 tmp |= L1CSR1_ICFI | L1CSR1_ICLFR; in flush_instruction_cache()
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| /openbmc/linux/arch/powerpc/kernel/ |
| H A D | cpu_setup_e500.S | 26 ori r0, r0, (L1CSR1_ICFI | L1CSR1_ICLFR | L1CSR1_ICE)
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| /openbmc/linux/arch/powerpc/kvm/ |
| H A D | e500_emulate.c | 254 vcpu_e500->l1csr1 &= ~(L1CSR1_ICFI | L1CSR1_ICLFR); in kvmppc_core_emulate_mtspr_e500()
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| /openbmc/linux/arch/powerpc/include/asm/ |
| H A D | reg_booke.h | 589 #define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */ macro
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| /openbmc/u-boot/arch/powerpc/include/asm/ |
| H A D | processor.h | 494 #define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */ macro
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| /openbmc/qemu/target/ppc/ |
| H A D | cpu.h | 2307 #define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */ macro
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