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Searched refs:L1CSR1_ICE (Results 1 – 7 of 7) sorted by relevance

/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Drelease.S110 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
111 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
116 andi. r1,r3,L1CSR1_ICE@l
H A Dstart.S779 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
780 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
785 andi. r1,r3,L1CSR1_ICE@l
942 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
943 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
1378 ori r4,r4,(L1CSR1_CPE | L1CSR1_ICE)@l
1379 oris r4,r4,(L1CSR1_CPE | L1CSR1_ICE)@h
1388 ori r3,r3,L1CSR1_ICE
1397 andi. r3,r3,L1CSR1_ICE
/openbmc/linux/arch/powerpc/kernel/
H A Dcpu_setup_e500.S23 andi. r3, r0, L1CSR1_ICE
26 ori r0, r0, (L1CSR1_ICFI | L1CSR1_ICLFR | L1CSR1_ICE)
/openbmc/linux/arch/powerpc/include/asm/
H A Dreg_booke.h591 #define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */ macro
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dprocessor.h496 #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ macro
/openbmc/qemu/target/ppc/
H A Dcpu.h2306 #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ macro
H A Dtranslate.c1179 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); in spr_write_e500_l1csr1()