Searched refs:L1CSR1_CPE (Results 1 – 7 of 7) sorted by relevance
| /openbmc/u-boot/arch/powerpc/cpu/mpc85xx/ |
| H A D | release.S | 110 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
111 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
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| H A D | start.S | 779 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
780 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
942 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
943 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
1378 ori r4,r4,(L1CSR1_CPE | L1CSR1_ICE)@l
1379 oris r4,r4,(L1CSR1_CPE | L1CSR1_ICE)@h
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| /openbmc/linux/arch/powerpc/kernel/ |
| H A D | cpu_setup_e500.S | 25 oris r0, r0, L1CSR1_CPE@h
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| /openbmc/linux/arch/powerpc/include/asm/ |
| H A D | reg_booke.h | 588 #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */ macro
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| /openbmc/u-boot/arch/powerpc/include/asm/ |
| H A D | processor.h | 492 #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */ macro
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| /openbmc/qemu/target/ppc/ |
| H A D | cpu.h | 2305 #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */ macro
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| H A D | translate.c | 1179 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); in spr_write_e500_l1csr1()
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