Searched refs:L1CSR0_DCE (Results 1 – 7 of 7) sorted by relevance
| /openbmc/u-boot/arch/powerpc/cpu/mpc85xx/ |
| H A D | release.S | 128 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
129 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
134 andi. r1,r3,L1CSR0_DCE@l
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| H A D | start.S | 797 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
798 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
803 andi. r1,r3,L1CSR0_DCE@l
1407 ori r0,r0,(L1CSR0_CPE | L1CSR0_DCE)@l
1408 oris r0,r0,(L1CSR0_CPE | L1CSR0_DCE)@h
1419 ori r4,r4,L1CSR0_DCE
1428 andi. r3,r3,L1CSR0_DCE
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| /openbmc/linux/arch/powerpc/kernel/ |
| H A D | cpu_setup_e500.S | 33 andi. r3, r0, L1CSR0_DCE
48 ori r0, r0, L1CSR0_DCE
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| /openbmc/linux/arch/powerpc/include/asm/ |
| H A D | reg_booke.h | 585 #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ macro
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| /openbmc/u-boot/arch/powerpc/include/asm/ |
| H A D | processor.h | 490 #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ macro
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| /openbmc/qemu/target/ppc/ |
| H A D | cpu.h | 2303 #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ macro
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| H A D | translate.c | 1171 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); in spr_write_e500_l1csr0()
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