Searched refs:L1CSR0_CPE (Results 1 – 7 of 7) sorted by relevance
| /openbmc/u-boot/arch/powerpc/cpu/mpc85xx/ |
| H A D | release.S | 128 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
129 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
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| H A D | start.S | 797 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
798 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
1407 ori r0,r0,(L1CSR0_CPE | L1CSR0_DCE)@l
1408 oris r0,r0,(L1CSR0_CPE | L1CSR0_DCE)@h
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| /openbmc/linux/arch/powerpc/kernel/ |
| H A D | cpu_setup_e500.S | 47 oris r0, r0, L1CSR0_CPE@h
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| /openbmc/linux/arch/powerpc/include/asm/ |
| H A D | reg_booke.h | 580 #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */ macro
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| /openbmc/u-boot/arch/powerpc/include/asm/ |
| H A D | processor.h | 486 #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */ macro
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| /openbmc/qemu/target/ppc/ |
| H A D | cpu.h | 2299 #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */ macro
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| H A D | translate.c | 1171 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); in spr_write_e500_l1csr0()
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