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Searched refs:KSEG1 (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/arch/mips/include/asm/mach-lantiq/falcon/
H A Dlantiq_soc.h34 #define FALCON_CHIPID ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x0c))
35 #define FALCON_CHIPTYPE ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x38))
36 #define FALCON_CHIPCONF ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x40))
/openbmc/linux/arch/mips/include/asm/
H A Daddrspace.h81 #define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1)
89 #define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1)
99 #define KSEG1 0xa0000000 macro
/openbmc/linux/arch/mips/lantiq/falcon/
H A Dreset.c25 #define BOOT_REG_BASE (KSEG1 | 0x1F200000)
31 #define WDT_REG_BASE (KSEG1 | 0x1F8803F0)
H A Dprom.c34 #define BOOT_REG_BASE (KSEG1 | 0x1F200000)
/openbmc/u-boot/arch/mips/include/asm/
H A Daddrspace.h78 #define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1)
86 #define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1)
96 #define KSEG1 0xa0000000 macro
/openbmc/u-boot/arch/mips/mach-ath79/
H A Ddram.c16 gd->ram_size = get_ram_size((void *)KSEG1, SZ_256M); in dram_init()
/openbmc/linux/arch/mips/rb532/
H A Dsetup.c50 set_io_port_base(KSEG1); in plat_mem_setup()
/openbmc/linux/arch/mips/include/asm/mach-lantiq/xway/
H A Dlantiq_soc.h94 #define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
/openbmc/linux/arch/mips/lantiq/
H A Dprom.c76 set_io_port_base((unsigned long) KSEG1); in plat_mem_setup()
/openbmc/linux/arch/mips/ralink/
H A Dof.c91 set_io_port_base(KSEG1); in plat_mem_setup()
/openbmc/linux/arch/mips/ath79/
H A Dsetup.c215 set_io_port_base(KSEG1); in plat_mem_setup()
/openbmc/linux/arch/mips/txx9/rbtx4927/
H A Dsetup.c224 set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET); in rbtx4927_mem_setup()
/openbmc/linux/arch/mips/
H A DKconfig1068 # KSEG1 and the implementation specific "uncached accelerated" used