1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2d41ced01SJohn Crispin /* 3d41ced01SJohn Crispin * 497b92108SJohn Crispin * Copyright (C) 2010 John Crispin <john@phrozen.org> 5d41ced01SJohn Crispin */ 6d41ced01SJohn Crispin 7d41ced01SJohn Crispin #ifndef _LTQ_FALCON_H__ 8d41ced01SJohn Crispin #define _LTQ_FALCON_H__ 9d41ced01SJohn Crispin 10d41ced01SJohn Crispin #ifdef CONFIG_SOC_FALCON 11d41ced01SJohn Crispin 12d41ced01SJohn Crispin #include <linux/pinctrl/pinctrl.h> 13d41ced01SJohn Crispin #include <lantiq.h> 14d41ced01SJohn Crispin 15d41ced01SJohn Crispin /* Chip IDs */ 16d41ced01SJohn Crispin #define SOC_ID_FALCON 0x01B8 17d41ced01SJohn Crispin 18d41ced01SJohn Crispin /* SoC Types */ 19d41ced01SJohn Crispin #define SOC_TYPE_FALCON 0x01 20d41ced01SJohn Crispin 21d41ced01SJohn Crispin /* 22d41ced01SJohn Crispin * during early_printk no ioremap possible at this early stage 234939788eSRalf Baechle * let's use KSEG1 instead 24d41ced01SJohn Crispin */ 25d41ced01SJohn Crispin #define LTQ_ASC0_BASE_ADDR 0x1E100C00 26d41ced01SJohn Crispin #define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC0_BASE_ADDR) 27d41ced01SJohn Crispin 28d41ced01SJohn Crispin /* WDT */ 29d41ced01SJohn Crispin #define LTQ_RST_CAUSE_WDTRST 0x0002 30d41ced01SJohn Crispin 31d41ced01SJohn Crispin /* CHIP ID */ 32d41ced01SJohn Crispin #define LTQ_STATUS_BASE_ADDR 0x1E802000 33d41ced01SJohn Crispin 34d41ced01SJohn Crispin #define FALCON_CHIPID ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x0c)) 35d41ced01SJohn Crispin #define FALCON_CHIPTYPE ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x38)) 36d41ced01SJohn Crispin #define FALCON_CHIPCONF ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x40)) 37d41ced01SJohn Crispin 38d41ced01SJohn Crispin /* SYSCTL - start/stop/restart/configure/... different parts of the Soc */ 39d41ced01SJohn Crispin #define SYSCTL_SYS1 0 40d41ced01SJohn Crispin #define SYSCTL_SYSETH 1 41d41ced01SJohn Crispin #define SYSCTL_SYSGPE 2 42d41ced01SJohn Crispin 43d41ced01SJohn Crispin /* BOOT_SEL - find what boot media we have */ 44d41ced01SJohn Crispin #define BS_FLASH 0x1 45d41ced01SJohn Crispin #define BS_SPI 0x4 46d41ced01SJohn Crispin 47d41ced01SJohn Crispin /* global register ranges */ 48d41ced01SJohn Crispin extern __iomem void *ltq_ebu_membase; 49d41ced01SJohn Crispin extern __iomem void *ltq_sys1_membase; 50d41ced01SJohn Crispin #define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y)) 51d41ced01SJohn Crispin #define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x)) 52d41ced01SJohn Crispin 53d41ced01SJohn Crispin #define ltq_sys1_w32(x, y) ltq_w32((x), ltq_sys1_membase + (y)) 54d41ced01SJohn Crispin #define ltq_sys1_r32(x) ltq_r32(ltq_sys1_membase + (x)) 55d41ced01SJohn Crispin #define ltq_sys1_w32_mask(clear, set, reg) \ 56d41ced01SJohn Crispin ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg) 57d41ced01SJohn Crispin 58e316cb2bSJohn Crispin /* allow the gpio and pinctrl drivers to talk to eachother */ 59e316cb2bSJohn Crispin extern int pinctrl_falcon_get_range_size(int id); 60e316cb2bSJohn Crispin extern void pinctrl_falcon_add_gpio_range(struct pinctrl_gpio_range *range); 61e316cb2bSJohn Crispin 62d41ced01SJohn Crispin /* 63d41ced01SJohn Crispin * to keep the irq code generic we need to define this to 0 as falcon 64d41ced01SJohn Crispin * has no EIU/EBU 65d41ced01SJohn Crispin */ 66d41ced01SJohn Crispin #define LTQ_EBU_PCC_ISTAT 0 67d41ced01SJohn Crispin 68d41ced01SJohn Crispin #endif /* CONFIG_SOC_FALCON */ 69d41ced01SJohn Crispin #endif /* _LTQ_XWAY_H__ */ 70