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Searched refs:IPU_CHA_DB_MODE_SEL (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/drivers/video/
H A Dipu_common.c544 __raw_readl(IPU_CHA_DB_MODE_SEL(0))); in ipu_dump_registers()
546 __raw_readl(IPU_CHA_DB_MODE_SEL(32))); in ipu_dump_registers()
696 reg = __raw_readl(IPU_CHA_DB_MODE_SEL(in_dma)); in ipu_uninit_channel()
697 __raw_writel(reg & ~idma_mask(in_dma), IPU_CHA_DB_MODE_SEL(in_dma)); in ipu_uninit_channel()
698 reg = __raw_readl(IPU_CHA_DB_MODE_SEL(out_dma)); in ipu_uninit_channel()
699 __raw_writel(reg & ~idma_mask(out_dma), IPU_CHA_DB_MODE_SEL(out_dma)); in ipu_uninit_channel()
1044 reg = __raw_readl(IPU_CHA_DB_MODE_SEL(dma_chan)); in ipu_init_channel_buffer()
1049 __raw_writel(reg, IPU_CHA_DB_MODE_SEL(dma_chan)); in ipu_init_channel_buffer()
H A Dmx3fb.c103 #define IPU_CHA_DB_MODE_SEL (0x0C + IPU_BASE) macro
561 reg = readl(IPU_CHA_DB_MODE_SEL); in ipu_init_channel_buffer()
563 writel(reg, IPU_CHA_DB_MODE_SEL); in ipu_init_channel_buffer()
H A Dipu_regs.h311 #define IPU_CHA_DB_MODE_SEL(ch) (&IPU_CM_REG->ch_db_mode_sel[ch / 32]) macro
/openbmc/linux/drivers/gpu/ipu-v3/
H A Dipu-common.c280 reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num)); in ipu_idmac_set_double_buffer()
285 ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num)); in ipu_idmac_set_double_buffer()
575 val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num)); in ipu_idmac_disable_channel()
577 ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num)); in ipu_idmac_disable_channel()
1289 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0))); in ipu_dump()
1291 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(32))); in ipu_dump()
H A Dipu-prv.h53 #define IPU_CHA_DB_MODE_SEL(ch) IPU_CM_REG(0x0150 + 4 * ((ch) / 32)) macro