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Searched refs:IOADDR (Results 1 – 25 of 30) sorted by relevance

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/openbmc/linux/arch/mips/sibyte/common/
H A Dsb_tbprof.c152 __raw_writeq(0, IOADDR(A_SCD_PERF_CNT_1)); in arm_tb()
164 IOADDR(A_BCM1480_SCD_PERF_CNT_CFG0)); in arm_tb()
169 IOADDR(A_BCM1480_SCD_PERF_CNT_CFG1)); in arm_tb()
176 IOADDR(A_SCD_PERF_CNT_CFG)); in arm_tb()
200 IOADDR(A_SCD_TRACE_CFG)); in sbprof_tb_intr()
222 IOADDR(A_SCD_TRACE_CFG)); in sbprof_tb_intr()
276 IOADDR(A_SCD_PERF_CNT_CFG)); in sbprof_zbprof_start()
304 __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_0)); in sbprof_zbprof_start()
305 __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_1)); in sbprof_zbprof_start()
333 IOADDR(A_SCD_TRACE_SEQUENCE_0)); in sbprof_zbprof_start()
[all …]
H A Dbus_watcher.c73 status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS_DEBUG)); in check_bus_watcher()
77 status = csr_in32(IOADDR(A_BCM1480_BUS_ERR_STATUS_DEBUG)); in check_bus_watcher()
87 l2_err = csr_in32(IOADDR(A_BUS_L2_ERRORS)); in check_bus_watcher()
88 memio_err = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS)); in check_bus_watcher()
166 (long long)__raw_readq(IOADDR(A_SCD_TRACE_READ))); in sibyte_bw_int()
168 csr_out32(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); in sibyte_bw_int()
173 stats->status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS)); in sibyte_bw_int()
176 stats->l2_err = cntr = csr_in32(IOADDR(A_BUS_L2_ERRORS)); in sibyte_bw_int()
181 csr_out32(0, IOADDR(A_BUS_L2_ERRORS)); in sibyte_bw_int()
187 csr_out32(0, IOADDR(A_BUS_MEM_IO_ERRORS)); in sibyte_bw_int()
[all …]
/openbmc/linux/arch/mips/sibyte/sb1250/
H A Dirq.c47 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + in sb1250_mask_irq()
50 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + in sb1250_mask_irq()
61 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + in sb1250_unmask_irq()
64 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + in sb1250_unmask_irq()
88 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) + in sb1250_set_affinity()
100 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + in sb1250_set_affinity()
103 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + in sb1250_set_affinity()
156 IOADDR(A_IMR_REGISTER(cpu, in ack_sb1250_irq()
231 IOADDR(A_IMR_REGISTER(0, in arch_init_irq()
235 IOADDR(A_IMR_REGISTER(1, in arch_init_irq()
[all …]
H A Dsmp.c21 IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_SET_CPU),
22 IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_SET_CPU)
26 IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CLR_CPU),
27 IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CLR_CPU)
31 IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CPU),
32 IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CPU)
H A Dsetup.c175 sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION)); in sb1250_setup()
184 plldiv = G_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG))); in sb1250_setup()
/openbmc/linux/arch/mips/sibyte/bcm1480/
H A Dsmp.c26 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
27 IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
28 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
29 IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
33 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
34 IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
35 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
40 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
41 IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
42 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
[all …]
H A Dirq.c157 pending = __raw_readq(IOADDR(A_BCM1480_IMR_REGISTER(bcm1480_irq_owner[irq], in ack_bcm1480_irq()
168 __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(cpu_logical_map(i), in ack_bcm1480_irq()
249 IOADDR(A_BCM1480_IMR_REGISTER(cpu, in arch_init_irq()
258 IOADDR(A_BCM1480_IMR_REGISTER(cpu, in arch_init_irq()
271 __raw_writeq(IMR_IP3_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + in arch_init_irq()
279 IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_0_CLR_CPU))); in arch_init_irq()
281 IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_1_CLR_CPU))); in arch_init_irq()
288 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_H))); in arch_init_irq()
292 __raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_L))); in arch_init_irq()
320 IOADDR(base + R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H)); in dispatch_ip2()
[all …]
H A Dsetup.c110 sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION)); in bcm1480_setup()
120 plldiv = G_BCM1480_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG))); in bcm1480_setup()
/openbmc/u-boot/include/configs/
H A Dxtfpga.h138 #define CONFIG_SYS_FPGAREG_DATE IOADDR(0x0D020000)
150 #define CONFIG_SYS_FPGAREG_FREQ IOADDR(0x0D020004) /* CPU clock frequency*/
159 #define CONFIG_SYS_FPGAREG_DIPSW IOADDR(0x0D02000C)
170 #define CONFIG_SYS_FPGAREG_RESET IOADDR(0x0D020010) /* Reset board .. */
179 #define CONFIG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */
190 #define CONFIG_SYS_ETHOC_BASE IOADDR(0x0d030000)
191 #define CONFIG_SYS_ETHOC_BUFFER_ADDR IOADDR(0x0D800000)
203 # define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000)
209 # define CONFIG_SYS_FLASH_BASE IOADDR(0x00000000)
210 # define CONFIG_SYS_MONITOR_BASE IOADDR(0x06000000)
[all …]
/openbmc/linux/arch/mips/kernel/
H A Dcevt-bcm1480.c36 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); in sibyte_set_periodic()
37 init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); in sibyte_set_periodic()
50 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); in sibyte_shutdown()
62 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); in sibyte_next_event()
63 init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); in sibyte_next_event()
85 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); in sibyte_counter_handler()
130 IOADDR(A_BCM1480_IMR_REGISTER(cpu, in sb1480_clockevent_init()
H A Dcevt-sb1250.c33 cfg = IOADDR(A_SCD_TIMER_REGISTER(smp_processor_id(), R_SCD_TIMER_CFG)); in sibyte_shutdown()
46 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); in sibyte_set_periodic()
47 init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); in sibyte_set_periodic()
61 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); in sibyte_next_event()
62 init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); in sibyte_next_event()
84 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); in sibyte_counter_handler()
130 IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) + in sb1250_clockevent_init()
H A Dcsrc-sb1250.c29 addr = IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CNT)); in sb1250_hpt_get_cycles()
59 IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, in sb1250_clocksource_init()
62 IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, in sb1250_clocksource_init()
65 IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, in sb1250_clocksource_init()
H A Dcsrc-bcm1480.c21 return (u64) __raw_readq(IOADDR(A_SCD_ZBBUS_CYCLE_COUNT)); in bcm1480_hpt_read()
34 return __raw_readq(IOADDR(A_SCD_ZBBUS_CYCLE_COUNT)); in sb1480_read_sched_clock()
43 plldiv = G_BCM1480_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG))); in sb1480_clocksource_init()
/openbmc/linux/arch/xtensa/platforms/xt2000/include/platform/
H A Dserial.h22 #define DUART16552_1_ADDR IOADDR(0x0d050020) /* channel 1 */
23 #define DUART16552_2_ADDR IOADDR(0x0d050000) /* channel 2 */
H A Dhardware.h25 #define SONIC83934_ADDR IOADDR(0x0d030000)
41 #define XT2000_LED_ADDR IOADDR(0x0d040000)
/openbmc/linux/arch/mips/mm/
H A Dcerr-sb1.c139 status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS)); in check_bus_watcher()
142 l2_err = csr_in32(IOADDR(A_BUS_L2_ERRORS)); in check_bus_watcher()
144 l2_tag = in64(IOADDR(A_L2_ECC_TAG)); in check_bus_watcher()
146 memio_err = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS)); in check_bus_watcher()
172 csr_out32(M_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG)); in sb1_cache_error()
H A Dpage.c642 __raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT))); in clear_page()
648 while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG))) in clear_page()
651 __raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); in clear_page()
669 __raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT))); in copy_page()
675 while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG))) in copy_page()
678 __raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); in copy_page()
/openbmc/u-boot/arch/xtensa/include/asm/
H A Daddrspace.h25 #define IOADDR(x) (CONFIG_SYS_IO_BASE + (x)) macro
/openbmc/linux/arch/xtensa/platforms/xtfpga/include/platform/
H A Dhardware.h40 #define XTFPGA_FPGAREGS_VADDR IOADDR(0x0D020000)
/openbmc/linux/arch/mips/include/asm/sibyte/
H A Dsb1250.h52 #define IOADDR(a) ((void __iomem *)(IO_BASE + (a))) macro
/openbmc/linux/arch/xtensa/include/asm/
H A Dio.h23 #define IOADDR(x) (XCHAL_KIO_BYPASS_VADDR + (x)) macro
/openbmc/linux/arch/xtensa/platforms/xtfpga/
H A Dlcd.c21 #define LCD_INSTR_ADDR ((char *)IOADDR(CONFIG_XTFPGA_LCD_BASE_ADDR))
/openbmc/linux/arch/mips/sibyte/swarm/
H A Dsetup.c155 reg = IOADDR(LEDS_PHYS) + 0x20 + ((3 - i) << 3); in setleds()
/openbmc/linux/arch/mips/pci/
H A Dpci-sb1250.c219 reg = __raw_readq(IOADDR(A_SCD_SYSTEM_CFG)); in sb1250_pcibios_init()
H A Dpci-bcm1480.c210 reg = __raw_readq(IOADDR(A_SCD_SYSTEM_CFG)); in bcm1480_pcibios_init()

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