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Searched refs:INREG (Results 1 – 16 of 16) sorted by relevance

/openbmc/linux/drivers/video/fbdev/aty/
H A Dradeon_pm.c338 if ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) > CFG_ATI_REV_A13) in radeon_pm_enable_dynamic_mode()
421 if (INREG(MEM_CNTL) & R300_MEM_USE_CD_CH_ONLY) in radeon_pm_enable_dynamic_mode()
473 ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) || in radeon_pm_enable_dynamic_mode()
475 ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) <= CFG_ATI_REV_A13))) { in radeon_pm_enable_dynamic_mode()
491 ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) in radeon_pm_enable_dynamic_mode()
502 ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) { in radeon_pm_enable_dynamic_mode()
558 return INREG( MC_IND_DATA); in INMC()
573 rinfo->save_regs[9] = INREG(DISP_MISC_CNTL); in radeon_pm_save_regs()
574 rinfo->save_regs[10] = INREG(DISP_PWR_MAN); in radeon_pm_save_regs()
575 rinfo->save_regs[11] = INREG(LVDS_GEN_CNTL); in radeon_pm_save_regs()
[all …]
H A Dradeon_base.c292 (void)INREG(CLOCK_CNTL_DATA); in radeon_pll_errata_after_index_slow()
293 (void)INREG(CRTC_GEN_CNTL); in radeon_pll_errata_after_index_slow()
304 save = INREG(CLOCK_CNTL_INDEX); in radeon_pll_errata_after_data_slow()
307 tmp = INREG(CLOCK_CNTL_DATA); in radeon_pll_errata_after_data_slow()
318 tmp = INREG(addr); in _OUTREGP()
331 data = INREG(CLOCK_CNTL_DATA); in __INPLL()
360 if ((INREG(RBBM_STATUS) & 0x7f) >= entries) in _radeon_fifo_wait()
382 if (!(INREG(DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) in radeon_engine_flush()
397 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { in _radeon_engine_idle()
429 temp = INREG(MPP_TB_CONFIG); in radeon_map_ROM()
[all …]
H A Dradeon_accel.c30 local_base = INREG(MC_FB_LOCATION) << 16; in radeon_fixup_offset()
201 clock_cntl_index = INREG(CLOCK_CNTL_INDEX); in radeonfb_engine_reset()
212 host_path_cntl = INREG(HOST_PATH_CNTL); in radeonfb_engine_reset()
213 rbbm_soft_reset = INREG(RBBM_SOFT_RESET); in radeonfb_engine_reset()
222 INREG(RBBM_SOFT_RESET); in radeonfb_engine_reset()
224 tmp = INREG(RB2D_DSTCACHE_MODE); in radeonfb_engine_reset()
235 INREG(RBBM_SOFT_RESET); in radeonfb_engine_reset()
244 INREG(RBBM_SOFT_RESET); in radeonfb_engine_reset()
248 INREG(HOST_PATH_CNTL); in radeonfb_engine_reset()
269 OUTREG(RB2D_DSTCACHE_MODE, INREG(RB2D_DSTCACHE_MODE) | in radeonfb_engine_init()
[all …]
H A Dradeon_i2c.c24 val = INREG(chan->ddc_reg) & ~(VGA_DDC_CLK_OUT_EN); in radeon_gpio_setscl()
29 (void)INREG(chan->ddc_reg); in radeon_gpio_setscl()
38 val = INREG(chan->ddc_reg) & ~(VGA_DDC_DATA_OUT_EN); in radeon_gpio_setsda()
43 (void)INREG(chan->ddc_reg); in radeon_gpio_setsda()
52 val = INREG(chan->ddc_reg); in radeon_gpio_getscl()
63 val = INREG(chan->ddc_reg); in radeon_gpio_getsda()
157 (INREG(LVDS_GEN_CNTL) & LVDS_ON)) { in radeon_probe_i2c_connector()
H A Dradeon_monitor.c325 ulOrigCRTC_EXT_CNTL = INREG(CRTC_EXT_CNTL); in radeon_crt_is_connected()
330 ulOrigDAC_EXT_CNTL = INREG(DAC_EXT_CNTL); in radeon_crt_is_connected()
344 ulOrigDAC_CNTL = INREG(DAC_CNTL); in radeon_crt_is_connected()
354 ulData = INREG(DAC_CNTL); in radeon_crt_is_connected()
567 ((rinfo->bios_seg && (INREG(BIOS_4_SCRATCH) & 4)) in radeon_probe_screens()
568 || (INREG(LVDS_GEN_CNTL) & LVDS_ON))) { in radeon_probe_screens()
850 u32 tmp = INREG(FP_HORZ_STRETCH) & HORZ_PANEL_SIZE; in radeon_check_modes()
852 tmp = INREG(FP_VERT_STRETCH) & VERT_PANEL_SIZE; in radeon_check_modes()
H A Dradeon_backlight.c65 lvds_gen_cntl = INREG(LVDS_GEN_CNTL); in radeon_bl_update_status()
H A Dradeonfb.h380 #define INREG(addr) readl((rinfo->mmio_base)+addr) macro
/openbmc/linux/drivers/video/fbdev/intelfb/
H A Dintelfbhw.c284 if (INREG(LVDS) & PORT_ENABLE) in intelfbhw_check_non_crt()
286 if (INREG(DVOA) & PORT_ENABLE) in intelfbhw_check_non_crt()
288 if (INREG(DVOB) & PORT_ENABLE) in intelfbhw_check_non_crt()
290 if (INREG(DVOC) & PORT_ENABLE) in intelfbhw_check_non_crt()
425 tmp = INREG(DSPACNTR); in intelfbhw_do_blank()
432 tmp = INREG(DSPABASE); in intelfbhw_do_blank()
449 tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK; in intelfbhw_do_blank()
529 hw->vga0_divisor = INREG(VGA0_DIVISOR); in intelfbhw_read_hw_state()
530 hw->vga1_divisor = INREG(VGA1_DIVISOR); in intelfbhw_read_hw_state()
531 hw->vga_pd = INREG(VGAPD); in intelfbhw_read_hw_state()
[all …]
H A Dintelfb_i2c.c62 val = INREG(chan->reg); in intelfb_gpio_setscl()
73 val = INREG(chan->reg); in intelfb_gpio_setsda()
84 val = INREG(chan->reg); in intelfb_gpio_getscl()
96 val = INREG(chan->reg); in intelfb_gpio_getsda()
H A Dintelfbhw.h525 #define INREG(addr) readl((u32 __iomem *)(dinfo->mmio_base + (addr))) macro
553 head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK; \
554 tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK; \
H A Dintelfbdrv.c1346 OUTREG(DPLL_A, INREG(DPLL_A) & ~DPLL_VCO_ENABLE); in intelfb_set_par()
1567 if (INREG(CURSOR_A_BASEADDR) != physical) { in intelfb_cursor()
/openbmc/u-boot/drivers/video/
H A Dati_radeon_fb.h70 #define INREG(addr) readl((rinfo->mmio_base)+addr) macro
78 tmp = INREG(addr); in _OUTREGP()
98 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) in radeon_engine_flush()
110 if ((INREG(RBBM_STATUS) & 0x7f) >= entries) in _radeon_fifo_wait()
125 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { in _radeon_engine_idle()
252 data = INREG(CLOCK_CNTL_DATA); in __INPLL()
H A Dati_radeon_fb.c113 u32 tom = INREG(NB_TOM); in radeon_identify_vram()
123 OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000); in radeon_identify_vram()
134 tmp = INREG(CONFIG_MEMSIZE); in radeon_identify_vram()
159 (INREG(MEM_SDRAM_MODE_REG) & (1<<30))) in radeon_identify_vram()
164 tmp = INREG(MEM_CNTL); in radeon_identify_vram()
576 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16; in radeon_probe()
/openbmc/qemu/target/hexagon/
H A Dmacros.h201 #define fEXTRACTU_BITS(INREG, WIDTH, OFFSET) \ argument
202 ((WIDTH) ? extract64((INREG), (OFFSET), (WIDTH)) : 0LL)
203 #define fEXTRACTU_BIDIR(INREG, WIDTH, OFFSET) \ argument
204 (fZXTN(WIDTH, 32, fBIDIR_LSHIFTR((INREG), (OFFSET), 4_8)))
205 #define fEXTRACTU_RANGE(INREG, HIBIT, LOWBIT) \ argument
207 extract64((INREG), (LOWBIT), ((HIBIT) - (LOWBIT) + 1)) : \
209 #define fINSERT_RANGE(INREG, HIBIT, LOWBIT, INVAL) \ argument
212 INREG = (width >= 0 ? \
213 deposit64((INREG), (LOWBIT), width, (INVAL)) : \
214 INREG); \
/openbmc/qemu/target/hexagon/idef-parser/
H A Dmacros.h.inc84 #define fEXTRACTU_BIDIR(INREG, WIDTH, OFFSET) \
85 (fZXTN(WIDTH, 32, fBIDIR_LSHIFTR((INREG), (OFFSET), 4_8)))
/openbmc/qemu/target/hexagon/imported/
H A Dmacros.def79 (fZXTN(WIDTH,32,(INREG >> OFFSET))),
85 (fZXTN(WIDTH,32,fBIDIR_LSHIFTR((INREG),(OFFSET),4_8))),
91 (fZXTN((HIBIT-LOWBIT+1),32,(INREG >> LOWBIT))),
102 INREG &= ~(((fCONSTLL(1)<<width)-1)<<offset);
104 INREG |= ((INVAL & ((fCONSTLL(1)<<width)-1)) << offset);