Searched refs:IMX8ULP_CLK_SPLL3_PFD3_DIV1 (Results 1 – 3 of 3) sorted by relevance
28 #define IMX8ULP_CLK_SPLL3_PFD3_DIV1 21 macro
427 assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1>,429 assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1>;
193 …clks[IMX8ULP_CLK_SPLL3_PFD3_DIV1] = imx_clk_hw_divider("spll3_pfd3_div1", "spll3_pfd3_div1_gate", … in imx8ulp_clk_cgc1_init()