Searched refs:IMX8ULP_CLK_SOSC_DIV2 (Results 1 – 3 of 3) sorted by relevance
38 #define IMX8ULP_CLK_SOSC_DIV2 31 macro
238 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
210 …clks[IMX8ULP_CLK_SOSC_DIV2] = imx_clk_hw_divider("sosc_div2", "sosc_div2_gate", base + 0x108, 8, 6… in imx8ulp_clk_cgc1_init()