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Searched refs:IMM (Results 1 – 9 of 9) sorted by relevance

/openbmc/qemu/target/hexagon/idef-parser/
H A Dmacros.h.inc96 #define fPCALIGN(IMM) (IMM = IMM & ~3)
107 #define fEA_RI(REG, IMM) (EA = REG + IMM)
109 #define fEA_IRs(IMM, REG, SCALE) (EA = IMM + (REG << SCALE))
110 #define fEA_IMM(IMM) (EA = IMM)
113 #define fEA_GPI(IMM) (EA = fREAD_GP() + IMM)
114 #define fPM_I(REG, IMM) (REG = REG + IMM)
H A Didef-parser.y60 %token <rvalue> REG IMM PRED
191 var_decl : var_type IMM
251 | IMM
326 | IMM '=' rvalue
337 | LOAD '(' IMM ',' IMM ',' SIGN ',' var ',' lvalue ')'
346 | STORE '(' IMM ',' IMM ',' var ',' rvalue ')'
436 for_statement : FOR '(' IMM '=' IMM ';' IMM '<' IMM ';' IMM PLUSPLUS ')'
474 | IMM
587 | SAT '(' IMM ',' rvalue ')'
678 | SXT '(' rvalue ',' IMM ',' rvalue ')'
[all …]
H A DREADME.rst206 | IMM
684 | IMM
/openbmc/qemu/target/hexagon/
H A Dmacros.h312 #define fIMMEXT(IMM) (IMM = IMM) argument
313 #define fMUST_IMMEXT(IMM) fIMMEXT(IMM) argument
315 #define fPCALIGN(IMM) IMM = (IMM & ~PCALIGN_MASK) argument
427 #define fEA_RI(REG, IMM) tcg_gen_addi_tl(EA, REG, IMM) argument
434 #define fEA_IRs(IMM, REG, SCALE) \ argument
437 tcg_gen_addi_tl(EA, EA, IMM); \
440 #define fEA_RI(REG, IMM) \ argument
442 EA = REG + IMM; \
448 #define fEA_IRs(IMM, REG, SCALE) \ argument
450 EA = IMM + (REG << SCALE); \
[all …]
/openbmc/qemu/target/hexagon/imported/
H A Dmacros.def324 (IMM = IMM),
330 fIMMEXT(IMM),
336 IMM=(IMM & ~PCALIGN_MASK),
870 do { EA=REG+IMM; fDOCHKPAGECROSS(REG,EA); } while (0),
882 do { EA=IMM+(REG<<SCALE); fDOCHKPAGECROSS(IMM,EA); } while (0),
888 EA=IMM,
906 do { EA=fREAD_GP()+IMM; fGP_DOCHKPAGECROSS(fREAD_GP(),EA); } while (0),
912 do { REG = REG + IMM; } while (0),
1536 {sys_pause(thread, insn->slot, IMM);},
1542 …p exception, PCYCLE=%lld TYPE=%d NPC=%x IMM=0x%x",thread->processor_ptr->pstats[pcycles],TRAPTYPE,…
[all …]
/openbmc/openbmc/meta-openembedded/meta-networking/recipes-daemons/opensaf/opensaf/
H A D0001-immom_python-convert-to-python3.patch26 immom -- An IMM Object Manager in Python
/openbmc/qemu/target/microblaze/
H A Dinsns.decode29 # Include any IMM prefix in the value reported.
/openbmc/qemu/target/arm/tcg/
H A Dt32.decode410 # At v6T2, this is the T5 encoding of SUBS PC, LR, #IMM, and works as for
411 # every other encoding of SUBS. With v7VE, IMM=0 is redefined as ERET.
/openbmc/qemu/target/ppc/translate/
H A Dvsx-impl.c.inc679 #define TCG_OP_IMM_i64(FUNC, OP, IMM) \
682 OP(t, b, IMM); \