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Searched refs:ICR1 (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/drivers/irqchip/
H A Dirq-renesas-rza1.c29 #define ICR1 2 /* Interrupt Control Register 1 */ macro
95 tmp = readw_relaxed(priv->base + ICR1); in rza1_irqc_set_type()
98 writew_relaxed(tmp, priv->base + ICR1); in rza1_irqc_set_type()
/openbmc/u-boot/arch/sh/include/asm/
H A Dcpu_sh7720.h48 #define ICR1 0xA4140010 macro
H A Dcpu_sh7780.h42 #define ICR1 0xFFD0001C macro
H A Dcpu_sh7722.h44 #define ICR1 0xA414001C macro
/openbmc/u-boot/arch/arm/include/asm/arch-imx/
H A Dimx-regs.h121 #define ICR1(x) __REG2(IMX_GPIO_BASE + 0x28, ((x) & 3) << 8) macro