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Searched refs:ICR (Results 1 – 25 of 41) sorted by relevance

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/openbmc/linux/drivers/net/wireless/ath/wil6210/
H A Dinterrupt.c295 offsetof(struct RGF_ICR, ICR)); in wil6210_irq_rx()
357 offsetof(struct RGF_ICR, ICR)); in wil6210_irq_rx_edma()
408 offsetof(struct RGF_ICR, ICR)); in wil6210_irq_tx_edma()
454 offsetof(struct RGF_ICR, ICR)); in wil6210_irq_tx()
542 offsetof(struct RGF_ICR, ICR)); in wil6210_irq_misc()
688 offsetof(struct RGF_ICR, ICR)); in wil6210_debug_irq_mask()
696 offsetof(struct RGF_ICR, ICR)); in wil6210_debug_irq_mask()
705 offsetof(struct RGF_ICR, ICR)); in wil6210_debug_irq_mask()
713 offsetof(struct RGF_ICR, ICR)); in wil6210_debug_irq_mask()
722 offsetof(struct RGF_ICR, ICR)); in wil6210_debug_irq_mask()
[all …]
/openbmc/qemu/hw/char/
H A Dstm32l4x5_usart.c138 REG32(ICR, 0x20)
139 FIELD(ICR, WUCF, 20, 1) /* Wakeup from Stop mode clear flag */
140 FIELD(ICR, CMCF, 17, 1) /* Character match clear flag */
141 FIELD(ICR, EOBCF, 12, 1) /* End of block clear flag */
142 FIELD(ICR, RTOCF, 11, 1) /* Receiver timeout clear flag */
143 FIELD(ICR, CTSCF, 9, 1) /* CTS clear flag */
144 FIELD(ICR, LBDCF, 8, 1) /* LIN break detection clear flag */
146 FIELD(ICR, TCCF, 6, 1) /* Transmission complete clear flag */
147 FIELD(ICR, IDLECF, 4, 1) /* Idle line detected clear flag */
148 FIELD(ICR, ORECF, 3, 1) /* Overrun error clear flag */
[all …]
/openbmc/qemu/target/tricore/
H A Dcpu.h98 FIELD(ICR, IE_161, 15, 1)
99 FIELD(ICR, IE_13, 8, 1)
100 FIELD(ICR, PIPN, 16, 8)
101 FIELD(ICR, CCPN, 0, 8)
H A Dhelper.c187 FIELD_GETTER_WITH_FEATURE(icr_get_ie, ICR, IE, 161)
188 FIELD_SETTER_WITH_FEATURE(icr_set_ie, ICR, IE, 161)
189 FIELD_GETTER(icr_get_ccpn, ICR, CCPN)
190 FIELD_SETTER(icr_set_ccpn, ICR, CCPN)
H A Dgdbstub.c52 return env->ICR; in tricore_cpu_gdb_read_csfr()
90 env->ICR = val; in tricore_cpu_gdb_write_csfr()
H A Dcsfr.h.inc17 A(0xfe2c, ICR, TRICORE_FEATURE_13)
/openbmc/linux/sound/pcmcia/vx/
H A Dvxp_ops.c153 vx_outb(chip, ICR, 0); in vxp_load_xilinx_binary()
161 vx_outb(chip, ICR, ICR_HF1); in vxp_load_xilinx_binary()
177 vx_outb(chip, ICR, 0); in vxp_load_xilinx_binary()
193 vx_outb(chip, ICR, ICR_HF0); in vxp_load_xilinx_binary()
318 vx_outb(chip, ICR, do_write ? ICR_TREQ : ICR_RREQ); in vx_setup_pseudo_dma()
343 vx_outb(chip, ICR, 0); in vx_release_pseudo_dma()
427 vx_outb(chip, ICR, 0); in vxp_dma_read()
/openbmc/qemu/hw/net/
H A De1000e_core.c160 if (timer->core->mac[IMS] & timer->core->mac[ICR]) { in e1000e_intrmgr_on_throttling_timer()
2001 trace_e1000e_irq_icr_clear_eiac(core->mac[ICR], core->mac[EIAC]); in e1000e_msix_notify_one()
2005 core->mac[ICR] &= ~effective_eiac; in e1000e_msix_notify_one()
2089 core->mac[ICR] &= ~E1000_ICR_ASSERTED; in e1000e_fix_icr_asserted()
2090 if (core->mac[ICR]) { in e1000e_fix_icr_asserted()
2091 core->mac[ICR] |= E1000_ICR_ASSERTED; in e1000e_fix_icr_asserted()
2094 trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]); in e1000e_fix_icr_asserted()
2101 uint32_t old_causes = core->mac[IMS] & core->mac[ICR]; in e1000e_raise_interrupts()
2111 if (core->mac[ICR] & E1000_ICR_OTHER_CAUSES) { in e1000e_raise_interrupts()
2112 core->mac[ICR] |= E1000_ICR_OTHER; in e1000e_raise_interrupts()
[all …]
H A Digb_core.c908 igb_raise_interrupts(core, ICR, E1000_ICR_TXDW); in igb_start_xmit()
2100 igb_raise_interrupts(core, ICR, causes); in igb_receive_internal()
2160 igb_raise_interrupts(core, ICR, E1000_ICR_LSC); in igb_core_set_link_status()
2278 core->mac[ICR] &= ~E1000_ICR_ASSERTED; in igb_fix_icr_asserted()
2279 if (core->mac[ICR]) { in igb_fix_icr_asserted()
2280 core->mac[ICR] |= E1000_ICR_ASSERTED; in igb_fix_icr_asserted()
2283 trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]); in igb_fix_icr_asserted()
2288 uint32_t old_causes = core->mac[ICR] & core->mac[IMS]; in igb_raise_interrupts()
2300 raised_causes = core->mac[ICR] & core->mac[IMS] & ~old_causes; in igb_raise_interrupts()
2325 raised_causes = core->mac[ICR] & core->mac[IMS] & ~old_causes; in igb_raise_interrupts()
[all …]
H A De1000.c281 s->mac_reg[ICR] = val; in set_interrupt_cause()
293 pending_ints = (s->mac_reg[IMS] & s->mac_reg[ICR]); in set_interrupt_cause()
348 set_interrupt_cause(s, 0, s->mac_reg[ICR]); in e1000_mit_timer()
354 DBGOUT(INTERRUPT, "set_ics %x, ICR %x, IMR %x\n", val, s->mac_reg[ICR], in set_ics()
356 set_interrupt_cause(s, 0, val | s->mac_reg[ICR]); in set_ics()
1034 uint32_t ret = s->mac_reg[ICR]; in mac_icr_read()
1113 set_interrupt_cause(s, 0, s->mac_reg[ICR] & ~val); in set_icr()
1165 [ICR] = mac_icr_read, [EECD] = get_eecd,
1193 [IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr,
1523 VMSTATE_UINT32(mac_reg[ICR], E1000State),
H A Dtrace-events165 e1000e_rx_interrupt_set(uint32_t causes) "Receive interrupt set (ICR causes %u)"
166 e1000e_rx_interrupt_delayed(uint32_t causes) "Receive interrupt delayed (ICR causes %u)"
207 e1000e_irq_pending_interrupts(uint32_t pending, uint32_t icr, uint32_t ims) "ICR PENDING: 0x%x (ICR…
208 e1000e_irq_write_ics(uint32_t val) "Adding ICR bits 0x%x"
212 e1000e_irq_icr_clear_nonmsix_icr_read(void) "Clearing ICR on read due to non MSI-X int"
213 e1000e_irq_icr_clear_zero_ims(void) "Clearing ICR on read due to zero IMS"
214 e1000e_irq_icr_clear_iame(void) "Clearing ICR on read due to IAME"
215 e1000e_irq_icr_clear_icr_bit_ims(uint32_t icr, uint32_t ims) "Clearing ICR on read due correspondin…
217 e1000e_irq_icr_clear_eiac(uint32_t icr, uint32_t eiac) "Clearing ICR bits due to EIAC, ICR: 0x%X, E…
281 igb_irq_icr_clear_gpie_nsicr(void) "Clearing ICR on read due to GPIE.NSICR enabled"
H A De1000_common.h33 defreg(GPTC), defreg(ICR), defreg(ICS), defreg(IMC),
H A Digb_common.h61 defreg(GPTC), defreg(ICR), defreg(ICS), defreg(IMC),
/openbmc/qemu/hw/timer/
H A Davr_timer16.c104 #define ICR(t16) VAL16(t16->icrl, t16->icrh) macro
207 if (ICR(t16) < alarm_offset && ICR(t16) > CNT(t16)) { in avr_timer16_set_alarm()
208 alarm_offset = ICR(t16); in avr_timer16_set_alarm()
/openbmc/qemu/rust/hw/char/pl011/src/
H A Dlib.rs110 ICR = 0x044, enumerator
140 case! { DR, RSR, FR, FBRD, ILPR, IBRD, LCR_H, CR, FLS, IMSC, RIS, MIS, ICR, DMACR } in try_from()
H A Ddevice.rs225 Ok(ICR) => { in read()
313 Ok(ICR) => { in write()
/openbmc/u-boot/arch/sh/include/asm/
H A Dcpu_sh7750.h117 #define ICR 0xFFD00000 macro
/openbmc/linux/sound/pci/vx222/
H A Dvx222_ops.c225 vx_outl(chip, ICR, do_write ? ICR_TREQ : ICR_RREQ); in vx2_setup_pseudo_dma()
239 vx_outl(chip, ICR, 0); in vx2_release_pseudo_dma()
/openbmc/qemu/tests/qtest/
H A Dstm32l4x5_usart-test.c45 REG32(ICR, 0x20)
/openbmc/u-boot/include/
H A Dppc_asm.tmpl87 #define ICR 148 /* Interrupt Cause Register (37-44) */
/openbmc/linux/Documentation/virt/kvm/x86/
H A Dhypercalls.rst150 - a3: APIC ICR
/openbmc/u-boot/arch/powerpc/cpu/mpc8xx/
H A Dstart.S81 mfspr r3, ICR /* clear Interrupt Cause Register */
/openbmc/linux/drivers/bluetooth/
H A Dbtnxpuart.c260 #define ICR 0x000000c7 macro
673 uart_config.icr.value = __cpu_to_le32(ICR); in nxp_fw_change_baudrate()
/openbmc/linux/arch/m68k/include/asm/
H A DMC68EZ328.h208 #define ICR WORD_REF(ICR_ADDR) macro
H A DMC68328.h246 #define ICR WORD_REF(ICR_ADDR) macro

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