| /openbmc/qemu/hw/char/ |
| H A D | stm32l4x5_usart.c | 138 REG32(ICR, 0x20)
139 FIELD(ICR, WUCF, 20, 1) /* Wakeup from Stop mode clear flag */
140 FIELD(ICR, CMCF, 17, 1) /* Character match clear flag */
141 FIELD(ICR, EOBCF, 12, 1) /* End of block clear flag */
142 FIELD(ICR, RTOCF, 11, 1) /* Receiver timeout clear flag */
143 FIELD(ICR, CTSCF, 9, 1) /* CTS clear flag */
144 FIELD(ICR, LBDCF, 8, 1) /* LIN break detection clear flag */
146 FIELD(ICR, TCCF, 6, 1) /* Transmission complete clear flag */
147 FIELD(ICR, IDLECF, 4, 1) /* Idle line detected clear flag */
148 FIELD(ICR, ORECF, 3, 1) /* Overrun error clear flag */
[all …]
|
| /openbmc/qemu/target/tricore/ |
| H A D | cpu.h | 103 FIELD(ICR, IE_161, 15, 1)
104 FIELD(ICR, IE_13, 8, 1)
105 FIELD(ICR, PIPN, 16, 8)
106 FIELD(ICR, CCPN, 0, 8)
|
| H A D | gdbstub.c | 52 return env->ICR; in tricore_cpu_gdb_read_csfr()
90 env->ICR = val; in tricore_cpu_gdb_write_csfr()
|
| H A D | csfr.h.inc | 17 A(0xfe2c, ICR, TRICORE_FEATURE_13)
|
| /openbmc/qemu/hw/timer/ |
| H A D | avr_timer16.c | 104 #define ICR(t16) VAL16(t16->icrl, t16->icrh) macro
207 if (ICR(t16) < alarm_offset && ICR(t16) > CNT(t16)) { in avr_timer16_set_alarm()
208 alarm_offset = ICR(t16); in avr_timer16_set_alarm()
|
| /openbmc/u-boot/arch/sh/include/asm/ |
| H A D | cpu_sh7750.h | 117 #define ICR 0xFFD00000 macro
|
| /openbmc/qemu/hw/net/ |
| H A D | e1000.c | 279 s->mac_reg[ICR] = val; in set_interrupt_cause()
291 pending_ints = (s->mac_reg[IMS] & s->mac_reg[ICR]); in set_interrupt_cause()
346 set_interrupt_cause(s, 0, s->mac_reg[ICR]); in e1000_mit_timer()
352 DBGOUT(INTERRUPT, "set_ics %x, ICR %x, IMR %x\n", val, s->mac_reg[ICR], in set_ics()
354 set_interrupt_cause(s, 0, val | s->mac_reg[ICR]); in set_ics()
1032 uint32_t ret = s->mac_reg[ICR]; in mac_icr_read()
1111 set_interrupt_cause(s, 0, s->mac_reg[ICR] & ~val); in set_icr()
1163 [ICR] = mac_icr_read, [EECD] = get_eecd,
1191 [IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr,
1512 VMSTATE_UINT32(mac_reg[ICR], E1000State),
|
| H A D | e1000_common.h | 33 defreg(GPTC), defreg(ICR), defreg(ICS), defreg(IMC),
|
| H A D | igb_common.h | 61 defreg(GPTC), defreg(ICR), defreg(ICS), defreg(IMC),
|
| /openbmc/qemu/tests/qtest/ |
| H A D | stm32l4x5_usart-test.c | 45 REG32(ICR, 0x20)
|
| /openbmc/u-boot/include/ |
| H A D | ppc_asm.tmpl | 87 #define ICR 148 /* Interrupt Cause Register (37-44) */
|
| /openbmc/u-boot/arch/powerpc/cpu/mpc8xx/ |
| H A D | start.S | 81 mfspr r3, ICR /* clear Interrupt Cause Register */
|
| /openbmc/u-boot/drivers/net/ |
| H A D | e1000.c | 1692 E1000_READ_REG(hw, ICR); in e1000_reset_hw()
|