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Searched refs:ICPU_SW_MODE_SW_SPI_CS_M (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/drivers/spi/
H A Dmscc_bb_spi.c83 value &= ~ICPU_SW_MODE_SW_SPI_CS_M; in mscc_bb_spi_cs_deactivate()
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/luton/
H A Dluton_icpu_cfg.h55 #define ICPU_SW_MODE_SW_SPI_CS_M GENMASK(8, 5) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
H A Docelot_icpu_cfg.h55 #define ICPU_SW_MODE_SW_SPI_CS_M GENMASK(8, 5) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/serval/
H A Dserval_icpu_cfg.h51 #define ICPU_SW_MODE_SW_SPI_CS_M GENMASK(8, 5) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/jr2/
H A Djr2_icpu_cfg.h58 #define ICPU_SW_MODE_SW_SPI_CS_M GENMASK(8, 5) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/servalt/
H A Dservalt_icpu_cfg.h56 #define ICPU_SW_MODE_SW_SPI_CS_M GENMASK(8, 5) macro