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Searched refs:ICPU_RESET_MEM_RST_FORCE (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/arch/mips/mach-mscc/include/mach/
H A Dddr.h464 ICPU_RESET_MEM_RST_FORCE, BASE_CFG + ICPU_RESET); in hal_vcoreiii_ddr_reset_assert()
650 setbits_le32(BASE_CFG + ICPU_RESET, ICPU_RESET_MEM_RST_FORCE); in hal_vcoreiii_ddr_reset_assert()
747 clrbits_le32(BASE_CFG + ICPU_RESET, ICPU_RESET_MEM_RST_FORCE); in hal_vcoreiii_init_memctl()
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/luton/
H A Dluton_icpu_cfg.h17 #define ICPU_RESET_MEM_RST_FORCE BIT(0) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
H A Docelot_icpu_cfg.h17 #define ICPU_RESET_MEM_RST_FORCE BIT(0) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/serval/
H A Dserval_icpu_cfg.h17 #define ICPU_RESET_MEM_RST_FORCE BIT(0) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/jr2/
H A Djr2_icpu_cfg.h17 #define ICPU_RESET_MEM_RST_FORCE BIT(0) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/servalt/
H A Dservalt_icpu_cfg.h17 #define ICPU_RESET_MEM_RST_FORCE BIT(0) macro