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Searched refs:ICPU_MEMCTRL_TIMING3 (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/arch/mips/mach-mscc/include/mach/luton/
H A Dluton_icpu_cfg.h168 #define ICPU_MEMCTRL_TIMING3 0x254 macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
H A Docelot_icpu_cfg.h179 #define ICPU_MEMCTRL_TIMING3 0x130 macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/serval/
H A Dserval_icpu_cfg.h182 #define ICPU_MEMCTRL_TIMING3 0x128 macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/jr2/
H A Djr2_icpu_cfg.h189 #define ICPU_MEMCTRL_TIMING3 0x150 macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/servalt/
H A Dservalt_icpu_cfg.h187 #define ICPU_MEMCTRL_TIMING3 0x130 macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/
H A Dddr.h790 writel(MSCC_MEMPARM_TIMING3, BASE_CFG + ICPU_MEMCTRL_TIMING3); in hal_vcoreiii_init_memctl()