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Searched refs:ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/arch/mips/mach-mscc/include/mach/
H A Dddr.h266 ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(VC3_MPAR_tRRD - 1) | \
303 ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(VC3_MPAR_tRRD - 1) | \
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/luton/
H A Dluton_icpu_cfg.h145 #define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(x) (((x) << 8) & GENMASK(11, 8)) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
H A Docelot_icpu_cfg.h156 #define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(x) (((x) << 8) & GENMASK(11, 8)) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/serval/
H A Dserval_icpu_cfg.h159 #define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(x) (((x) << 8) & GENMASK(11, 8)) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/jr2/
H A Djr2_icpu_cfg.h166 #define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(x) (((x) << 8) & GENMASK(11, 8)) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/servalt/
H A Dservalt_icpu_cfg.h164 #define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(x) (((x) << 8) & GENMASK(11, 8)) macro