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Searched refs:ICPU_MEMCTRL_TIMING0 (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/arch/mips/mach-mscc/include/mach/
H A Dddr.h782 writel(MSCC_MEMPARM_TIMING0, BASE_CFG + ICPU_MEMCTRL_TIMING0); in hal_vcoreiii_init_memctl()
784 clrbits_le32(BASE_CFG + ICPU_MEMCTRL_TIMING0, ((1 << 20) - 1)); in hal_vcoreiii_init_memctl()
785 setbits_le32(BASE_CFG + ICPU_MEMCTRL_TIMING0, MSCC_MEMPARM_TIMING0); in hal_vcoreiii_init_memctl()
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/luton/
H A Dluton_icpu_cfg.h108 #define ICPU_MEMCTRL_TIMING0 0x248 macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
H A Docelot_icpu_cfg.h119 #define ICPU_MEMCTRL_TIMING0 0x124 macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/serval/
H A Dserval_icpu_cfg.h122 #define ICPU_MEMCTRL_TIMING0 0x11c macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/jr2/
H A Djr2_icpu_cfg.h129 #define ICPU_MEMCTRL_TIMING0 0x144 macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/servalt/
H A Dservalt_icpu_cfg.h127 #define ICPU_MEMCTRL_TIMING0 0x124 macro