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Searched refs:ICPU_MEMCTRL_MR1_VAL (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/arch/mips/mach-mscc/include/mach/luton/
H A Dluton_icpu_cfg.h187 #define ICPU_MEMCTRL_MR1_VAL 0x25c macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
H A Docelot_icpu_cfg.h198 #define ICPU_MEMCTRL_MR1_VAL 0x13c macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/serval/
H A Dserval_icpu_cfg.h212 #define ICPU_MEMCTRL_MR1_VAL 0x134 macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/jr2/
H A Djr2_icpu_cfg.h219 #define ICPU_MEMCTRL_MR1_VAL 0x15c macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/servalt/
H A Dservalt_icpu_cfg.h217 #define ICPU_MEMCTRL_MR1_VAL 0x13c macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/
H A Dddr.h792 writel(MSCC_MEMPARM_MR1, BASE_CFG + ICPU_MEMCTRL_MR1_VAL); in hal_vcoreiii_init_memctl()