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Searched refs:ICPU_MEMCTRL_MR0_VAL (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/arch/mips/mach-mscc/include/mach/luton/
H A Dluton_icpu_cfg.h185 #define ICPU_MEMCTRL_MR0_VAL 0x258 macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
H A Docelot_icpu_cfg.h196 #define ICPU_MEMCTRL_MR0_VAL 0x138 macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/serval/
H A Dserval_icpu_cfg.h210 #define ICPU_MEMCTRL_MR0_VAL 0x130 macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/jr2/
H A Djr2_icpu_cfg.h217 #define ICPU_MEMCTRL_MR0_VAL 0x158 macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/servalt/
H A Dservalt_icpu_cfg.h215 #define ICPU_MEMCTRL_MR0_VAL 0x138 macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/
H A Dddr.h791 writel(MSCC_MEMPARM_MR0, BASE_CFG + ICPU_MEMCTRL_MR0_VAL); in hal_vcoreiii_init_memctl()