Home
last modified time | relevance | path

Searched refs:ICPU_MEMCTRL_CFG_DDR_MODE (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/arch/mips/mach-mscc/include/mach/luton/
H A Dluton_icpu_cfg.h81 #define ICPU_MEMCTRL_CFG_DDR_MODE BIT(11) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
H A Docelot_icpu_cfg.h92 #define ICPU_MEMCTRL_CFG_DDR_MODE BIT(11) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/serval/
H A Dserval_icpu_cfg.h90 #define ICPU_MEMCTRL_CFG_DDR_MODE BIT(11) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/jr2/
H A Djr2_icpu_cfg.h97 #define ICPU_MEMCTRL_CFG_DDR_MODE BIT(11) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/servalt/
H A Dservalt_icpu_cfg.h95 #define ICPU_MEMCTRL_CFG_DDR_MODE BIT(11) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/
H A Dddr.h236 (VC3_MPAR_DDR3_MODE ? ICPU_MEMCTRL_CFG_DDR_MODE : 0) | \