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Searched refs:ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/arch/mips/mach-mscc/include/mach/luton/
H A Dluton_icpu_cfg.h77 #define ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA BIT(15) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
H A Docelot_icpu_cfg.h88 #define ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA BIT(15) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/serval/
H A Dserval_icpu_cfg.h86 #define ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA BIT(15) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/jr2/
H A Djr2_icpu_cfg.h93 #define ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA BIT(15) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/servalt/
H A Dservalt_icpu_cfg.h91 #define ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA BIT(15) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/
H A Dddr.h487 val |= ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA; in hal_vcoreiii_ddr_verified()