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Searched refs:ICLR (Results 1 – 9 of 9) sorted by relevance

/openbmc/linux/drivers/irqchip/
H A Dirq-sa11x0.c23 #define ICLR 0x08 /* IC Level Reg. */ macro
94 st->iclr = readl_relaxed(iobase + ICLR); in sa1100irq_suspend()
111 writel_relaxed(st->iclr, iobase + ICLR); in sa1100irq_resume()
158 writel_relaxed(0, iobase + ICLR); in sa11x0_init_irq_nodt()
/openbmc/linux/arch/arm/mach-pxa/
H A Dirq.c31 #define ICLR (0x008) macro
161 __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ in pxa_init_irq_common()
209 __raw_writel(0, base + ICLR); in pxa_irq_resume()
/openbmc/qemu/hw/arm/
H A Dpxa2xx_pic.c25 #define ICLR 0x08 /* Interrupt Controller Level register */ macro
151 case ICLR: /* Level register */ in pxa2xx_pic_mem_read()
191 case ICLR: /* Level register */ in pxa2xx_pic_mem_write()
220 [0x2] = ICLR,
H A Dstrongarm.c105 #define ICLR 0x08 macro
145 case ICLR: in strongarm_pic_mem_read()
169 case ICLR: in strongarm_pic_mem_write()
/openbmc/linux/arch/arm/mach-sa1100/
H A Dpm.c93 ICLR = 0; in sa11x0_pm_enter()
/openbmc/u-boot/arch/arm/cpu/pxa/
H A Dpxa2xx.c218 writel(0, ICLR); in pxa_interrupt_setup()
/openbmc/linux/arch/arm/mach-sa1100/include/mach/
H A DSA-1100.h1212 #define ICLR __REG(0x90050008) /* IC Level Reg. */ macro
/openbmc/u-boot/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h1140 #define ICLR 0x40D00008 /* Interrupt Controller Level Register */ macro
/openbmc/u-boot/include/
H A DSA-1100.h1638 #define ICLR /* IC Level Reg. */ \ macro