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Searched refs:HW (Results 1 – 25 of 79) sorted by relevance

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/openbmc/u-boot/board/toradex/apalis_imx6/
H A DKconfig43 bool "Apalis iMX6 V1.0 HW"
45 Apalis iMX6 V1.0 HW has a different pinout for the UART.
49 option the config block stating V1.0 HW selects DCE mode,
/openbmc/u-boot/doc/device-tree-bindings/reset/
H A Dreset.txt21 in hardware for a reset signal to affect multiple logically separate HW blocks
23 the DT node of each affected HW block, since if activated, an unrelated block
26 children of the bus are affected by the reset signal, or an individual HW
28 appropriate software access to the reset signals in order to manage the HW,
29 rather than to slavishly enumerate the reset signal that affects each HW
/openbmc/u-boot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-core.h97 #define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW)
180 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
192 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
203 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
222 .flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS), \
/openbmc/u-boot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-core.h97 #define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW)
180 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
192 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
203 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
222 .flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS), \
/openbmc/u-boot/doc/device-tree-bindings/gpio/
H A Dnvidia,tegra186-gpio.txt11 package balls is under the control of a separate pin controller HW block. Two
30 Tegra HW documentation describes a unified naming convention for all GPIOs
44 matches the HW documentation. The values chosen for the names are alphabetically
46 IDs and HW register offsets using a lookup table.
51 of the number of ports it implements. Note that the HW documentation refers to
52 both the overall controller HW module and the sets-of-ports as "controllers".
89 The interrupt outputs from the HW block, one per set of ports, in the
90 order the HW manual describes them. The number of entries required varies
/openbmc/u-boot/doc/device-tree-bindings/net/
H A Dsnps,dwc-qos-ethernet.txt6 entries in properties are marked as optional, or only required in specific HW
25 The EQOS transmit path clock. The HW signal name is clk_tx_i.
30 The EQOS receive path clock. The HW signal name is clk_rx_i.
41 APB, AHB, AXI, etc. The HW signal name is hclk_i (AHB) or clk_csr_i (other
45 separate clock for the master and slave bus interfaces. The HW signal name
48 The PTP reference clock. The HW signal name is clk_ptp_ref_i.
91 - "eqos". The reset to the entire module. The HW signal name is hreset_n
/openbmc/qemu/docs/
H A Dqemupciserial.inf50 [ComPort_inst1.HW]
53 [ComPort_inst2.HW]
56 [ComPort_inst4.HW]
/openbmc/qemu/target/hexagon/imported/
H A Dbranch.idef208 /* HW Loop instructions */
211 Q6INSN(J2_loop0r,"loop0(#r7:2,Rs32)",ATTRIBS(),"Initialize HW loop 0",
217 Q6INSN(J2_loop1r,"loop1(#r7:2,Rs32)",ATTRIBS(),"Initialize HW loop 1",
222 Q6INSN(J2_loop0i,"loop0(#r7:2,#U10)",ATTRIBS(),"Initialize HW loop 0",
228 Q6INSN(J2_loop1i,"loop1(#r7:2,#U10)",ATTRIBS(),"Initialize HW loop 1",
234 Q6INSN(J2_ploop1sr,"p3=sp1loop0(#r7:2,Rs32)",ATTRIBS(A_ARCHV2),"Initialize HW loop 0",
240 Q6INSN(J2_ploop1si,"p3=sp1loop0(#r7:2,#U10)",ATTRIBS(A_ARCHV2),"Initialize HW loop 0",
247 Q6INSN(J2_ploop2sr,"p3=sp2loop0(#r7:2,Rs32)",ATTRIBS(A_ARCHV2),"Initialize HW loop 0",
253 Q6INSN(J2_ploop2si,"p3=sp2loop0(#r7:2,#U10)",ATTRIBS(A_ARCHV2),"Initialize HW loop 0",
260 Q6INSN(J2_ploop3sr,"p3=sp3loop0(#r7:2,Rs32)",ATTRIBS(A_ARCHV2),"Initialize HW loop 0",
[all …]
/openbmc/qemu/target/arm/tcg/
H A Dsme_helper.c1688 #define DO_MLALL(NAME, TYPEW, TYPEN, TYPEM, HW, HN, OP) \ argument
1697 d[HW(i)] = a[HW(i)] OP (nn * mm); \
1715 #define DO_MLALL_IDX(NAME, TYPEW, TYPEN, TYPEM, HW, HN, OP) \ argument
1727 d[HW(i + j)] = a[HW(i + j)] OP (nn * mm); \
1790 #define SQCVT2(NAME, TW, TN, HW, HN, SAT) \ argument
1801 d[HN(i)] = SAT(s0[HW(i)]); \
1802 d[HN(i + n)] = SAT(s1[HW(i)]); \
1815 #define SQCVT4(NAME, TW, TN, HW, HN, SAT) \ in SQCVT2() argument
1828 d[HN(i)] = SAT(s0[HW(i)]); \ in SQCVT2()
1829 d[HN(i + n)] = SAT(s1[HW(i)]); \ in SQCVT2()
[all …]
/openbmc/qemu/docs/specs/
H A Dacpi_hw_reduced_hotplug.rst5 The ACPI *Generic Event Device* (GED) is a HW reduced platform
11 GED allows HW reduced platforms to handle interrupts in ACPI ASL
/openbmc/qemu/docs/devel/
H A Dindex-tcg.rst8 are only implementing things for HW accelerated hypervisors.
/openbmc/qemu/docs/system/i386/
H A Dxenpvh.rst5 on HW virtualization features, emulation models and paravirtualization.
6 PVH is a mode that uses HW virtualization features (like HVM) but tries
/openbmc/phosphor-power/phosphor-regulators/docs/config_file/
H A Dcompare_vpd.md21 - HW
50 …cify one of the following: "CCIN", "Manufacturer", "Model", "PartNumber", "HW". …
/openbmc/u-boot/doc/
H A DREADME.omap368 To make U-Boot for OMAP3 support NAND device SW or HW ECC calculation, U-Boot
77 enables SW ECC calculation. HW ECC enabled with
82 executed by OMAP3's boot rom and therefore has to be written with HW ECC.
H A DREADME.N121315 - 3 HW-level nested interruptions.
/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/
H A D0001-qemu_measured_boot.c-ignore-TPM-error-and-continue-w.patch7 on HW, e.g. swtpm not started and/or configured with qemu,
/openbmc/docs/designs/
H A Dentity-manager-hw-id-vpd-discover-via-device-tree.md1 # Entity-Manager HW ID: VPD Discovery via Device-Tree Properties
11 BMC needs a process to identify and handle HPE GXP baseboards that provide HW ID
15 This proposal describes a method of handling for hardware where HW ID data is
20 Typical platforms provide HW ID data - often referred to as 'vital product data'
191 1. Not a 'usual' location for passing this kind HW-tied data. Unlikely to ever
194 2. Presenting HW-specific data here appears to go against the intended use of
334 rely on this service for Entity-Manager HW/config detection.
364 an Entity-Manager config's probe to trigger on match with a known HPE-HW
/openbmc/qemu/target/s390x/tcg/
H A Dinsn-data.h.inc41 C(0xb9c8, AHHHR, RRF_a, HW, r2_sr32, r3_sr32, new, r1_32h, add, adds32)
42 C(0xb9d8, AHHLR, RRF_a, HW, r2_sr32, r3, new, r1_32h, add, adds32)
51 C(0xcc08, AIH, RIL_a, HW, r1_sr32, i2, new, r1_32h, add, adds32)
71 C(0xb9ca, ALHHHR, RRF_a, HW, r2_sr32, r3_sr32, new, r1_32h, add, addu32)
72 C(0xb9da, ALHHLR, RRF_a, HW, r2_sr32, r3_32u, new, r1_32h, add, addu32)
82 C(0xcc0a, ALSIH, RIL_a, HW, r1_sr32, i2_32u, new, r1_32h, add, addu32)
83 C(0xcc0b, ALSIHN, RIL_a, HW, r1_sr32, i2_32u, new, r1_32h, add, 0)
138 C(0xcc06, BRCTH, RIL_b, HW, 0, 0, 0, 0, bcth, 0)
205 C(0xb9cd, CHHR, RRE, HW, r1_sr32, r2_sr32, 0, 0, 0, cmps32)
206 C(0xb9dd, CHLR, RRE, HW, r1_sr32, r2_o, 0, 0, 0, cmps32)
[all …]
/openbmc/u-boot/drivers/mailbox/
H A DKconfig9 CPU to another CPU, or sometimes to dedicated HW modules. They form
/openbmc/openbmc/meta-openembedded/meta-multimedia/recipes-multimedia/dvb-apps/files/dvb-scan-table/dvb-t/
H A Duk-Craigkelly3 # <http://www.digitaluk.co.uk/coveragechecker/main/tradeexport/KY3�9HW/NA/0/>
/openbmc/u-boot/doc/device-tree-bindings/i2c/
H A Dnvidia,tegra186-bpmp-i2c.txt3 In Tegra186, the BPMP (Boot and Power Management Processor) owns certain HW
/openbmc/openbmc/meta-arm/meta-arm/recipes-bsp/trusted-firmware-a/files/
H A D0001-qemu_measured_boot.c-ignore-TPM-error-and-continue-w.patch7 on HW, e.g. swtpm not started and/or configured with qemu,
/openbmc/u-boot/board/Arcturus/ucp1020/
H A DREADME26 HW Addresses.
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/nss/nss/
H A D0007-freebl-add-a-configure-option-to-disable-ARM-HW-cryp.patch4 Subject: [PATCH] freebl: add a configure option to disable ARM HW crypto
/openbmc/u-boot/drivers/led/
H A DKconfig17 LED HW controller accessed via MMIO registers.
18 HW blinking is supported and up to 24 LEDs can be controlled.
28 LED HW controller accessed via MMIO registers.
29 HW has no blinking capabilities and up to 32 LEDs can be controlled.

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