Searched refs:HIVE_ISP_DDR_WORD_BYTES (Results 1 – 14 of 14) sorted by relevance
31 #define DEBUG_DATA_BUF_MODE_DDR_ADDR HIVE_ISP_DDR_WORD_BYTES32 #define DEBUG_DATA_HEAD_DDR_ADDR (2 * HIVE_ISP_DDR_WORD_BYTES)33 #define DEBUG_DATA_TAIL_DDR_ADDR (3 * HIVE_ISP_DDR_WORD_BYTES)34 #define DEBUG_DATA_BUF_DDR_ADDR (4 * HIVE_ISP_DDR_WORD_BYTES)68 #ifdef HIVE_ISP_DDR_WORD_BYTES71 s8 padding1[HIVE_ISP_DDR_WORD_BYTES - sizeof(uint32_t)];73 s8 padding2[HIVE_ISP_DDR_WORD_BYTES - sizeof(uint32_t)];75 s8 padding3[HIVE_ISP_DDR_WORD_BYTES - sizeof(uint32_t)];77 s8 padding4[HIVE_ISP_DDR_WORD_BYTES - sizeof(uint32_t)];
443 unsigned int memory_alignment_in_bytes = HIVE_ISP_DDR_WORD_BYTES; in ia_css_csi2_calculate_input_system_alignment()466 memory_alignment_in_bytes = 2 * HIVE_ISP_DDR_WORD_BYTES; in ia_css_csi2_calculate_input_system_alignment()470 memory_alignment_in_bytes = HIVE_ISP_DDR_WORD_BYTES; in ia_css_csi2_calculate_input_system_alignment()
576 bytes_per_line = HIVE_ISP_DDR_WORD_BYTES * words_per_line; in calculate_stride()847 cfg->width = CEIL_DIV(cfg->stride, HIVE_ISP_DDR_WORD_BYTES); in calculate_isys2401_dma_port_cfg()
169 (HIVE_ISP_DDR_WORD_BYTES / SH_CSS_MORPH_TABLE_ELEM_BYTES)302 ((c_subsampling) * (num_chunks) * HIVE_ISP_DDR_WORD_BYTES)
57 , HIVE_ISP_DDR_WORD_BYTES)
31 #define HIVE_ISP_DDR_WORD_BYTES (HIVE_ISP_DDR_WORD_BITS / 8) macro39 #define CSS_DDR_WORD_BYTES HIVE_ISP_DDR_WORD_BYTES
415 my_css.mipi_frame_size[port] * HIVE_ISP_DDR_WORD_BYTES); in allocate_mipi_frames()
2163 me->dmem_size = CEIL_MUL(me->dmem_size, HIVE_ISP_DDR_WORD_BYTES); in ia_css_isp_3a_statistics_allocate()2164 me->vmem_size = CEIL_MUL(me->vmem_size, HIVE_ISP_DDR_WORD_BYTES); in ia_css_isp_3a_statistics_allocate()2165 me->hmem_size = CEIL_MUL(me->hmem_size, HIVE_ISP_DDR_WORD_BYTES); in ia_css_isp_3a_statistics_allocate()2615 HIVE_ISP_DDR_WORD_BYTES))); in sh_css_params_init()2626 HIVE_ISP_DDR_WORD_BYTES)); in sh_css_params_init()
8054 md->stride = CEIL_MUL(mdc->resolution.width, HIVE_ISP_DDR_WORD_BYTES); in metadata_info_init()
286 return CEIL_MUL(width, 2 * HIVE_ISP_DDR_WORD_BYTES); in ia_css_frame_pad_width()296 return CEIL_MUL(width, HIVE_ISP_DDR_WORD_BYTES); in ia_css_frame_pad_width()433 config->stride = HIVE_ISP_DDR_WORD_BYTES * words_per_line; in ia_css_dma_configure_from_info()493 stride = HIVE_ISP_DDR_WORD_BYTES * in frame_init_raw_single_plane()
34 #define XMEM_POW2_BYTES_PER_WORD HIVE_ISP_DDR_WORD_BYTES
239 HIVE_ISP_DDR_WORD_BYTES) / sizeof(*htemp_ptr); in ia_css_translate_dvs2_statistics()293 size = CEIL_MUL(sizeof(int) * grid->aligned_width, HIVE_ISP_DDR_WORD_BYTES) in ia_css_isp_dvs2_statistics_allocate()
328 HIVE_ISP_DDR_WORD_BYTES); in ia_css_isp_dvs_statistics_allocate()331 HIVE_ISP_DDR_WORD_BYTES); in ia_css_isp_dvs_statistics_allocate()
81 if ((init_dmem_cfg->ddr_data_addr % HIVE_ISP_DDR_WORD_BYTES) != 0) { in ia_css_spctrl_load_fw()