1f5fbb83fSMauro Carvalho Chehab /* SPDX-License-Identifier: GPL-2.0 */ 29d4fa1a1SMauro Carvalho Chehab /** 39d4fa1a1SMauro Carvalho Chehab Support for Intel Camera Imaging ISP subsystem. 49d4fa1a1SMauro Carvalho Chehab Copyright (c) 2010 - 2015, Intel Corporation. 59d4fa1a1SMauro Carvalho Chehab 69d4fa1a1SMauro Carvalho Chehab This program is free software; you can redistribute it and/or modify it 79d4fa1a1SMauro Carvalho Chehab under the terms and conditions of the GNU General Public License, 89d4fa1a1SMauro Carvalho Chehab version 2, as published by the Free Software Foundation. 99d4fa1a1SMauro Carvalho Chehab 109d4fa1a1SMauro Carvalho Chehab This program is distributed in the hope it will be useful, but WITHOUT 119d4fa1a1SMauro Carvalho Chehab ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 129d4fa1a1SMauro Carvalho Chehab FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 139d4fa1a1SMauro Carvalho Chehab more details. 149d4fa1a1SMauro Carvalho Chehab */ 159d4fa1a1SMauro Carvalho Chehab 169d4fa1a1SMauro Carvalho Chehab #ifndef _COMMON_ISP_CONST_H_ 179d4fa1a1SMauro Carvalho Chehab #define _COMMON_ISP_CONST_H_ 189d4fa1a1SMauro Carvalho Chehab 199d4fa1a1SMauro Carvalho Chehab /*#include "isp.h"*/ /* ISP_VEC_NELEMS */ 209d4fa1a1SMauro Carvalho Chehab 219d4fa1a1SMauro Carvalho Chehab /* Binary independent constants */ 229d4fa1a1SMauro Carvalho Chehab 239d4fa1a1SMauro Carvalho Chehab #ifndef NO_HOIST 249d4fa1a1SMauro Carvalho Chehab # define NO_HOIST HIVE_ATTRIBUTE((no_hoist)) 259d4fa1a1SMauro Carvalho Chehab #endif 269d4fa1a1SMauro Carvalho Chehab 279d4fa1a1SMauro Carvalho Chehab #define NO_HOIST_CSE HIVE_ATTRIBUTE((no_hoist, no_cse)) 289d4fa1a1SMauro Carvalho Chehab 299d4fa1a1SMauro Carvalho Chehab #define UNION struct /* Union constructors not allowed in C++ */ 309d4fa1a1SMauro Carvalho Chehab 319d4fa1a1SMauro Carvalho Chehab #define XMEM_WIDTH_BITS HIVE_ISP_DDR_WORD_BITS 329d4fa1a1SMauro Carvalho Chehab #define XMEM_SHORTS_PER_WORD (HIVE_ISP_DDR_WORD_BITS / 16) 339d4fa1a1SMauro Carvalho Chehab #define XMEM_INTS_PER_WORD (HIVE_ISP_DDR_WORD_BITS / 32) 349d4fa1a1SMauro Carvalho Chehab #define XMEM_POW2_BYTES_PER_WORD HIVE_ISP_DDR_WORD_BYTES 359d4fa1a1SMauro Carvalho Chehab 369d4fa1a1SMauro Carvalho Chehab #define BITS8_ELEMENTS_PER_XMEM_ADDR CEIL_DIV(XMEM_WIDTH_BITS, 8) 379d4fa1a1SMauro Carvalho Chehab #define BITS16_ELEMENTS_PER_XMEM_ADDR CEIL_DIV(XMEM_WIDTH_BITS, 16) 389d4fa1a1SMauro Carvalho Chehab 399d4fa1a1SMauro Carvalho Chehab #define ISP_NWAY_LOG2 6 409d4fa1a1SMauro Carvalho Chehab 419d4fa1a1SMauro Carvalho Chehab /* ***************************** 429d4fa1a1SMauro Carvalho Chehab * ISP input/output buffer sizes 439d4fa1a1SMauro Carvalho Chehab * ****************************/ 449d4fa1a1SMauro Carvalho Chehab /* input image */ 459d4fa1a1SMauro Carvalho Chehab #define INPUT_BUF_DMA_HEIGHT 2 469d4fa1a1SMauro Carvalho Chehab #define INPUT_BUF_HEIGHT 2 /* double buffer */ 479d4fa1a1SMauro Carvalho Chehab #define OUTPUT_BUF_DMA_HEIGHT 2 489d4fa1a1SMauro Carvalho Chehab #define OUTPUT_BUF_HEIGHT 2 /* double buffer */ 499d4fa1a1SMauro Carvalho Chehab #define OUTPUT_NUM_TRANSFERS 4 509d4fa1a1SMauro Carvalho Chehab 519d4fa1a1SMauro Carvalho Chehab /* GDC accelerator: Up/Down Scaling */ 529d4fa1a1SMauro Carvalho Chehab /* These should be moved to the gdc_defs.h in the device */ 539d4fa1a1SMauro Carvalho Chehab #define UDS_SCALING_N HRT_GDC_N 549d4fa1a1SMauro Carvalho Chehab /* AB: This should cover the zooming up to 16MP */ 559d4fa1a1SMauro Carvalho Chehab #define UDS_MAX_OXDIM 5000 569d4fa1a1SMauro Carvalho Chehab /* We support maximally 2 planes with different parameters 579d4fa1a1SMauro Carvalho Chehab - luma and chroma (YUV420) */ 589d4fa1a1SMauro Carvalho Chehab #define UDS_MAX_PLANES 2 599d4fa1a1SMauro Carvalho Chehab #define UDS_BLI_BLOCK_HEIGHT 2 609d4fa1a1SMauro Carvalho Chehab #define UDS_BCI_BLOCK_HEIGHT 4 619d4fa1a1SMauro Carvalho Chehab #define UDS_BLI_INTERP_ENVELOPE 1 629d4fa1a1SMauro Carvalho Chehab #define UDS_BCI_INTERP_ENVELOPE 3 639d4fa1a1SMauro Carvalho Chehab #define UDS_MAX_ZOOM_FAC 64 649d4fa1a1SMauro Carvalho Chehab /* Make it always one FPGA vector. 659d4fa1a1SMauro Carvalho Chehab Four FPGA vectors are required and 669d4fa1a1SMauro Carvalho Chehab four of them fit in one ASIC vector.*/ 679d4fa1a1SMauro Carvalho Chehab #define UDS_MAX_CHUNKS 16 689d4fa1a1SMauro Carvalho Chehab 699d4fa1a1SMauro Carvalho Chehab #define ISP_LEFT_PADDING _ISP_LEFT_CROP_EXTRA(ISP_LEFT_CROPPING) 709d4fa1a1SMauro Carvalho Chehab #define ISP_LEFT_PADDING_VECS CEIL_DIV(ISP_LEFT_PADDING, ISP_VEC_NELEMS) 719d4fa1a1SMauro Carvalho Chehab /* in case of continuous the croppong of the current binary doesn't matter for the buffer calculation, but the cropping of the sp copy should be used */ 729d4fa1a1SMauro Carvalho Chehab #define ISP_LEFT_PADDING_CONT _ISP_LEFT_CROP_EXTRA(SH_CSS_MAX_LEFT_CROPPING) 739d4fa1a1SMauro Carvalho Chehab #define ISP_LEFT_PADDING_VECS_CONT CEIL_DIV(ISP_LEFT_PADDING_CONT, ISP_VEC_NELEMS) 749d4fa1a1SMauro Carvalho Chehab 759d4fa1a1SMauro Carvalho Chehab #define CEIL_ROUND_DIV_STRIPE(width, stripe, padding) \ 769d4fa1a1SMauro Carvalho Chehab CEIL_MUL(padding + CEIL_DIV(width - padding, stripe), ((ENABLE_RAW_BINNING || ENABLE_FIXED_BAYER_DS) ? 4 : 2)) 779d4fa1a1SMauro Carvalho Chehab 789d4fa1a1SMauro Carvalho Chehab /* output (Y,U,V) image, 4:2:0 */ 799d4fa1a1SMauro Carvalho Chehab #define MAX_VECTORS_PER_LINE \ 809d4fa1a1SMauro Carvalho Chehab CEIL_ROUND_DIV_STRIPE(CEIL_DIV(ISP_MAX_INTERNAL_WIDTH, ISP_VEC_NELEMS), \ 819d4fa1a1SMauro Carvalho Chehab ISP_NUM_STRIPES, \ 829d4fa1a1SMauro Carvalho Chehab ISP_LEFT_PADDING_VECS) 839d4fa1a1SMauro Carvalho Chehab 849d4fa1a1SMauro Carvalho Chehab /* 859d4fa1a1SMauro Carvalho Chehab * ITERATOR_VECTOR_INCREMENT' explanation: 869d4fa1a1SMauro Carvalho Chehab * when striping an even number of iterations, one of the stripes is 879d4fa1a1SMauro Carvalho Chehab * one iteration wider than the other to account for overlap 889d4fa1a1SMauro Carvalho Chehab * so the calc for the output buffer vmem size is: 899d4fa1a1SMauro Carvalho Chehab * ((width[vectors]/num_of_stripes) + 2[vectors]) 909d4fa1a1SMauro Carvalho Chehab */ 919d4fa1a1SMauro Carvalho Chehab #define MAX_VECTORS_PER_OUTPUT_LINE \ 929d4fa1a1SMauro Carvalho Chehab CEIL_DIV(CEIL_DIV(ISP_MAX_OUTPUT_WIDTH, ISP_NUM_STRIPES) + ISP_LEFT_PADDING, ISP_VEC_NELEMS) 939d4fa1a1SMauro Carvalho Chehab 949d4fa1a1SMauro Carvalho Chehab /* Must be even due to interlaced bayer input */ 959d4fa1a1SMauro Carvalho Chehab #define MAX_VECTORS_PER_INPUT_LINE CEIL_MUL((CEIL_DIV(ISP_MAX_INPUT_WIDTH, ISP_VEC_NELEMS) + ISP_LEFT_PADDING_VECS), 2) 969d4fa1a1SMauro Carvalho Chehab #define MAX_VECTORS_PER_INPUT_STRIPE CEIL_ROUND_DIV_STRIPE(MAX_VECTORS_PER_INPUT_LINE, \ 979d4fa1a1SMauro Carvalho Chehab ISP_NUM_STRIPES, \ 989d4fa1a1SMauro Carvalho Chehab ISP_LEFT_PADDING_VECS) 999d4fa1a1SMauro Carvalho Chehab 1009d4fa1a1SMauro Carvalho Chehab /* Add 2 for left croppping */ 1019d4fa1a1SMauro Carvalho Chehab #define MAX_SP_RAW_COPY_VECTORS_PER_INPUT_LINE (CEIL_DIV(ISP_MAX_INPUT_WIDTH, ISP_VEC_NELEMS) + 2) 1029d4fa1a1SMauro Carvalho Chehab 1039d4fa1a1SMauro Carvalho Chehab #define MAX_VECTORS_PER_BUF_LINE \ 1049d4fa1a1SMauro Carvalho Chehab (MAX_VECTORS_PER_LINE + DUMMY_BUF_VECTORS) 1059d4fa1a1SMauro Carvalho Chehab #define MAX_VECTORS_PER_BUF_INPUT_LINE \ 1069d4fa1a1SMauro Carvalho Chehab (MAX_VECTORS_PER_INPUT_STRIPE + DUMMY_BUF_VECTORS) 1079d4fa1a1SMauro Carvalho Chehab #define MAX_OUTPUT_Y_FRAME_WIDTH \ 1089d4fa1a1SMauro Carvalho Chehab (MAX_VECTORS_PER_LINE * ISP_VEC_NELEMS) 1099d4fa1a1SMauro Carvalho Chehab #define MAX_OUTPUT_Y_FRAME_SIMDWIDTH \ 1109d4fa1a1SMauro Carvalho Chehab MAX_VECTORS_PER_LINE 1119d4fa1a1SMauro Carvalho Chehab #define MAX_OUTPUT_C_FRAME_WIDTH \ 1129d4fa1a1SMauro Carvalho Chehab (MAX_OUTPUT_Y_FRAME_WIDTH / 2) 1139d4fa1a1SMauro Carvalho Chehab #define MAX_OUTPUT_C_FRAME_SIMDWIDTH \ 1149d4fa1a1SMauro Carvalho Chehab CEIL_DIV(MAX_OUTPUT_C_FRAME_WIDTH, ISP_VEC_NELEMS) 1159d4fa1a1SMauro Carvalho Chehab 1169d4fa1a1SMauro Carvalho Chehab /* should be even */ 1179d4fa1a1SMauro Carvalho Chehab #define NO_CHUNKING (OUTPUT_NUM_CHUNKS == 1) 1189d4fa1a1SMauro Carvalho Chehab 1199d4fa1a1SMauro Carvalho Chehab #define MAX_VECTORS_PER_CHUNK \ 1209d4fa1a1SMauro Carvalho Chehab (NO_CHUNKING ? MAX_VECTORS_PER_LINE \ 1219d4fa1a1SMauro Carvalho Chehab : 2 * CEIL_DIV(MAX_VECTORS_PER_LINE, \ 1229d4fa1a1SMauro Carvalho Chehab 2 * OUTPUT_NUM_CHUNKS)) 1239d4fa1a1SMauro Carvalho Chehab 1249d4fa1a1SMauro Carvalho Chehab #define MAX_C_VECTORS_PER_CHUNK \ 1259d4fa1a1SMauro Carvalho Chehab (MAX_VECTORS_PER_CHUNK / 2) 1269d4fa1a1SMauro Carvalho Chehab 1279d4fa1a1SMauro Carvalho Chehab /* should be even */ 1289d4fa1a1SMauro Carvalho Chehab #define MAX_VECTORS_PER_OUTPUT_CHUNK \ 1299d4fa1a1SMauro Carvalho Chehab (NO_CHUNKING ? MAX_VECTORS_PER_OUTPUT_LINE \ 1309d4fa1a1SMauro Carvalho Chehab : 2 * CEIL_DIV(MAX_VECTORS_PER_OUTPUT_LINE, \ 1319d4fa1a1SMauro Carvalho Chehab 2 * OUTPUT_NUM_CHUNKS)) 1329d4fa1a1SMauro Carvalho Chehab 1339d4fa1a1SMauro Carvalho Chehab #define MAX_C_VECTORS_PER_OUTPUT_CHUNK \ 1349d4fa1a1SMauro Carvalho Chehab (MAX_VECTORS_PER_OUTPUT_CHUNK / 2) 1359d4fa1a1SMauro Carvalho Chehab 1369d4fa1a1SMauro Carvalho Chehab /* should be even */ 1379d4fa1a1SMauro Carvalho Chehab #define MAX_VECTORS_PER_INPUT_CHUNK \ 1389d4fa1a1SMauro Carvalho Chehab (INPUT_NUM_CHUNKS == 1 ? MAX_VECTORS_PER_INPUT_STRIPE \ 1399d4fa1a1SMauro Carvalho Chehab : 2 * CEIL_DIV(MAX_VECTORS_PER_INPUT_STRIPE, \ 1409d4fa1a1SMauro Carvalho Chehab 2 * OUTPUT_NUM_CHUNKS)) 1419d4fa1a1SMauro Carvalho Chehab 1429d4fa1a1SMauro Carvalho Chehab #define DEFAULT_C_SUBSAMPLING 2 1439d4fa1a1SMauro Carvalho Chehab 1449d4fa1a1SMauro Carvalho Chehab /****** DMA buffer properties */ 1459d4fa1a1SMauro Carvalho Chehab 1469d4fa1a1SMauro Carvalho Chehab #define RAW_BUF_LINES ((ENABLE_RAW_BINNING || ENABLE_FIXED_BAYER_DS) ? 4 : 2) 1479d4fa1a1SMauro Carvalho Chehab 1489d4fa1a1SMauro Carvalho Chehab /* [isp vmem] table size[vectors] per line per color (GR,R,B,GB), 1499d4fa1a1SMauro Carvalho Chehab multiples of NWAY */ 1509d4fa1a1SMauro Carvalho Chehab #define ISP2400_SCTBL_VECTORS_PER_LINE_PER_COLOR \ 151*83946783SMauro Carvalho Chehab CEIL_DIV(SH_CSS_MAX_SCTBL_WIDTH_PER_COLOR, ISP_VEC_NELEMS) 1529d4fa1a1SMauro Carvalho Chehab #define ISP2401_SCTBL_VECTORS_PER_LINE_PER_COLOR \ 153*83946783SMauro Carvalho Chehab CEIL_DIV(SH_CSS_MAX_SCTBL_WIDTH_PER_COLOR, ISP_VEC_NELEMS) 1549d4fa1a1SMauro Carvalho Chehab /* [isp vmem] table size[vectors] per line for 4colors (GR,R,B,GB), 1559d4fa1a1SMauro Carvalho Chehab multiples of NWAY */ 1569d4fa1a1SMauro Carvalho Chehab #define SCTBL_VECTORS_PER_LINE \ 1579d4fa1a1SMauro Carvalho Chehab (SCTBL_VECTORS_PER_LINE_PER_COLOR * IA_CSS_SC_NUM_COLORS) 1589d4fa1a1SMauro Carvalho Chehab 1599d4fa1a1SMauro Carvalho Chehab /*************/ 1609d4fa1a1SMauro Carvalho Chehab 1619d4fa1a1SMauro Carvalho Chehab /* Format for fixed primaries */ 1629d4fa1a1SMauro Carvalho Chehab 1639d4fa1a1SMauro Carvalho Chehab #define ISP_FIXED_PRIMARY_FORMAT IA_CSS_FRAME_FORMAT_NV12 1649d4fa1a1SMauro Carvalho Chehab 1659d4fa1a1SMauro Carvalho Chehab #endif /* _COMMON_ISP_CONST_H_ */ 166