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Searched refs:HIT_WRITEBACK_INV_SD (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/mips/lib/
H A Dcache.c130 cache_loop(start_addr, start_addr + size, slsize, HIT_WRITEBACK_INV_SD); in flush_cache()
155 cache_loop(start_addr, stop, slsize, HIT_WRITEBACK_INV_SD); in flush_dcache_range()
/openbmc/u-boot/arch/mips/include/asm/
H A Dcacheops.h80 #define HIT_WRITEBACK_INV_SD 0x17 macro