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Searched refs:HIT (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/arch/powerpc/perf/
H A Disa207-common.c223 ret = PH(LVL, L1) | LEVEL(L1) | P(SNOOP, HIT); in isa207_find_source()
226 ret = PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HIT); in isa207_find_source()
229 ret = PH(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); in isa207_find_source()
233 ret = P(SNOOP, HIT); in isa207_find_source()
238 ret |= P(LVL, HIT) | LEVEL(PMEM); in isa207_find_source()
242 ret |= P(LVL, HIT) | LEVEL(PMEM) | REM; in isa207_find_source()
252 ret |= P(SNOOP, HIT); in isa207_find_source()
260 ret |= PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HIT); in isa207_find_source()
264 ret |= PH(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); in isa207_find_source()
269 ret = PH(LVL, L2) | LEVEL(L2) | REM | P(SNOOP, HIT) | P(HOPS, 0); in isa207_find_source()
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H A Disa207-common.h275 #define PH(a, b) (P(LVL, HIT) | P(a, b))
/openbmc/linux/tools/perf/util/
H A Dmem-events.c583 if (lvl & P(LVL, HIT)) { in c2c_decode_stats()
606 if (snoop & P(SNOOP, HIT)) in c2c_decode_stats()
616 if (snoop & P(SNOOP, HIT)) in c2c_decode_stats()
626 if (snoop & P(SNOOP, HIT)) { in c2c_decode_stats()
648 if (lvl & P(LVL, HIT)) { in c2c_decode_stats()
/openbmc/linux/arch/x86/events/intel/
H A Dds.c73 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
86 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
88 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */
90 OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */
91 OP_LH | P(LVL, REM_RAM1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */
101 pebs_data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); in intel_pmu_pebs_data_source_nhm()
110 data_source[0x08] = OP_LH | pmem_or_l4 | P(SNOOP, HIT); in __intel_pmu_pebs_data_source_skl()
111 data_source[0x09] = OP_LH | pmem_or_l4 | REM | P(SNOOP, HIT); in __intel_pmu_pebs_data_source_skl()
124 data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); in __intel_pmu_pebs_data_source_grt()
192 val |= P(TLB, HIT); in precise_store_data()
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H A Dp4.c97 P4_ESCR_EMASK_BIT(P4_EVENT_ITLB_REFERENCE, HIT) |
547 [ C(RESULT_ACCESS) ] = P4_GEN_CACHE_EVENT(P4_EVENT_ITLB_REFERENCE, HIT,
/openbmc/qemu/hw/arm/
H A Dtrace-events19 …vmid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=%d vmid=%d add…
48 …uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache HIT for sid=0x%x (hits=…
/openbmc/linux/Documentation/admin-guide/device-mapper/
H A Dcache-policies.rst12 The policy can return a simple HIT or MISS or issue a migration.
/openbmc/linux/arch/x86/include/asm/
H A Dperf_event_p4.h605 P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, HIT, 0),
/openbmc/qemu/hw/timer/
H A Dtrace-events23 grlib_gptimer_hit(int id) "timer:%d HIT"
/openbmc/linux/drivers/iommu/
H A Dmsm_iommu_hw-8xxx.h611 #define SET_HIT(b, c, v) SET_CONTEXT_FIELD(b, c, V2PSR, HIT, v)
798 #define GET_HIT(b, c) GET_CONTEXT_FIELD(b, c, V2PSR, HIT)
1178 #define HIT (HIT_MASK << HIT_SHIFT) macro
/openbmc/linux/arch/x86/events/amd/
H A Dibs.c731 #define L(x) (PERF_MEM_S(LVL, x) | PERF_MEM_S(LVL, HIT))