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Searched refs:HHI_VID_PLL_CLK_DIV (Results 1 – 9 of 9) sorted by relevance

/openbmc/u-boot/drivers/video/meson/
H A Dmeson_vclk.c24 #define HHI_VID_PLL_CLK_DIV 0x1a0 /* 0x68 offset in data sheet */ macro
105 hhi_update_bits(HHI_VID_PLL_CLK_DIV, VID_PLL_EN, 0); in meson_vid_pll_set()
106 hhi_update_bits(HHI_VID_PLL_CLK_DIV, VID_PLL_PRESET, 0); in meson_vid_pll_set()
169 hhi_update_bits(HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
173 hhi_update_bits(HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
176 hhi_update_bits(HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
178 hhi_update_bits(HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
180 hhi_update_bits(HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
184 hhi_update_bits(HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
186 hhi_update_bits(HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
[all …]
/openbmc/linux/drivers/gpu/drm/meson/
H A Dmeson_vclk.c50 #define HHI_VID_PLL_CLK_DIV 0x1a0 /* 0x68 offset in data sheet */ macro
140 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_EN, 0); in meson_vid_pll_set()
141 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_PRESET, 0); in meson_vid_pll_set()
204 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
208 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
211 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
213 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
215 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
219 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
221 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-meson/
H A Dclock-axg.h68 #define HHI_VID_PLL_CLK_DIV 0x1a0 macro
H A Dclock-gx.h51 #define HHI_VID_PLL_CLK_DIV 0x1a0 /* 0x68 offset in data sheet */ macro
/openbmc/linux/drivers/clk/meson/
H A Daxg.h69 #define HHI_VID_PLL_CLK_DIV 0x1a0 macro
H A Dgxbb.h52 #define HHI_VID_PLL_CLK_DIV 0x1a0 /* 0x68 offset in data sheet */ macro
H A Dg12a.h69 #define HHI_VID_PLL_CLK_DIV 0x1A0 macro
H A Dgxbb.c1780 .reg_off = HHI_VID_PLL_CLK_DIV,
1785 .reg_off = HHI_VID_PLL_CLK_DIV,
1823 .offset = HHI_VID_PLL_CLK_DIV,
1842 .offset = HHI_VID_PLL_CLK_DIV,
H A Dg12a.c2642 .reg_off = HHI_VID_PLL_CLK_DIV,
2647 .reg_off = HHI_VID_PLL_CLK_DIV,
2668 .offset = HHI_VID_PLL_CLK_DIV,
2687 .offset = HHI_VID_PLL_CLK_DIV,