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Searched refs:HHI_HDMI_PLL_CNTL2 (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/drivers/video/meson/
H A Dmeson_vclk.c71 #define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */ macro
214 hhi_write(HHI_HDMI_PLL_CNTL2, 0x00404e00); in meson_venci_cvbs_clock_config()
223 hhi_write(HHI_HDMI_PLL_CNTL2, 0x800cb300); in meson_venci_cvbs_clock_config()
399 hhi_write(HHI_HDMI_PLL_CNTL2, in meson_hdmi_pll_set_params()
402 hhi_write(HHI_HDMI_PLL_CNTL2, in meson_hdmi_pll_set_params()
419 hhi_write(HHI_HDMI_PLL_CNTL2, 0x800cb000 | frac); in meson_hdmi_pll_set_params()
437 hhi_update_bits(HHI_HDMI_PLL_CNTL2, in meson_hdmi_pll_set_params()
445 hhi_update_bits(HHI_HDMI_PLL_CNTL2, in meson_hdmi_pll_set_params()
453 hhi_update_bits(HHI_HDMI_PLL_CNTL2, in meson_hdmi_pll_set_params()
/openbmc/linux/drivers/gpu/drm/meson/
H A Dmeson_vclk.c101 #define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */ macro
247 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00404e00); in meson_venci_cvbs_clock_config()
260 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb300); in meson_venci_cvbs_clock_config()
277 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00010000); in meson_venci_cvbs_clock_config()
499 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, in meson_hdmi_pll_set_params()
502 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, in meson_hdmi_pll_set_params()
519 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb000 | frac); in meson_hdmi_pll_set_params()
542 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, frac); in meson_hdmi_pll_set_params()
587 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2, in meson_hdmi_pll_set_params()
598 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2, in meson_hdmi_pll_set_params()
[all …]
/openbmc/linux/drivers/clk/meson/
H A Dgxbb.h98 #define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */ macro
H A Dg12a.h115 #define HHI_HDMI_PLL_CNTL2 0x328 macro
H A Dgxbb.c183 .reg_off = HHI_HDMI_PLL_CNTL2,
237 .reg_off = HHI_HDMI_PLL_CNTL2,
269 .offset = HHI_HDMI_PLL_CNTL2,
287 .offset = HHI_HDMI_PLL_CNTL2,
305 .offset = HHI_HDMI_PLL_CNTL2,
/openbmc/u-boot/arch/arm/include/asm/arch-meson/
H A Dclock-gx.h98 #define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */ macro