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Searched refs:HHI_GP0_PLL_CNTL5 (Results 1 – 8 of 8) sorted by relevance

/openbmc/u-boot/arch/arm/include/asm/arch-meson/
H A Dclock-axg.h22 #define HHI_GP0_PLL_CNTL5 0x50 macro
H A Dclock-gx.h23 #define HHI_GP0_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */ macro
/openbmc/linux/drivers/clk/meson/
H A Daxg.h23 #define HHI_GP0_PLL_CNTL5 0x50 macro
H A Dgxbb.h24 #define HHI_GP0_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */ macro
H A Dg12a.h29 #define HHI_GP0_PLL_CNTL5 0x054 macro
H A Daxg.c186 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 },
H A Dgxbb.c483 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 },
H A Dg12a.c1620 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x39272000 },