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Searched refs:HHI_GP0_PLL_CNTL3 (Results 1 – 8 of 8) sorted by relevance

/openbmc/u-boot/arch/arm/include/asm/arch-meson/
H A Dclock-axg.h20 #define HHI_GP0_PLL_CNTL3 0x48 macro
H A Dclock-gx.h21 #define HHI_GP0_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */ macro
/openbmc/linux/drivers/clk/meson/
H A Daxg.h21 #define HHI_GP0_PLL_CNTL3 0x48 macro
H A Dgxbb.h22 #define HHI_GP0_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */ macro
H A Dg12a.h27 #define HHI_GP0_PLL_CNTL3 0x04C macro
H A Dgxbb.c433 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a5590c4 },
481 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 },
H A Daxg.c184 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 },
H A Dg12a.c1618 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x48681c00 },